We present an integrated circuit fabricated in a process co-integrating CMOS and hafnium-oxide memristor technology, which provides a prototyping platform for projects involving memristors. Our circuit includes the periphery circuitry for using memristors within digital circuits, as well as an analog mode with direct access to memristors. The platform allows optimizing the conditions for reading and writing memristors, as well as developing and testing innovative memristor-based neuromorphic concepts.

The NimbleAI Horizon Europe project leverages key principles of energy-efficient visual sensing and processing in biological eyes and brains, and harnesses the latest advances in$\mathbf{33D}$stacked silicon integration, to create an integral sensing-processing neuromorphic architecture that efficiently and accurately runs computer vision algorithms in area-constrained endpoint chips. The rationale behind the NimbleAI architecture is: sense data only with high information value and discard data as soon as they are found not to be useful for the application (in a given context). The NimbleAI sensing-processing architecture is to be specialized after-deployment by tunning system-level trade-offs for each particular computer vision algorithm and deployment environment. The objectives of NimbleAI are: (1)$\mathbf{100x}$performance per mW gains compared to state-of-the-practice solutions (i.e., CPU/GPUs processing frame-based video); (2)$\mathbf{50x}$processing latency reduction compared to CPU/GPUs; (3) energy consumption in the order of tens of mWs; and (4) silicon area of approx. 50 mm2.

Bayesian reasoning is a machine learning approach that provides explainable outputs and excels in small-data situations with high uncertainty. However, it requires intensive memory access and computation and is, therefore, too energy-intensive for extreme edge contexts. Near-memory computation with memristors (or RRAM) can greatly improve the energy efficiency of its computations. Here, we report two fabricated integrated circuits in a hybrid CMOS-memristor process, featuring each sixteen tiny memristor arrays and the associated near-memory logic for Bayesian inference. One circuit performs Bayesian inference using stochastic computing, and the other uses logarithmic computation; these two paradigms fit the area constraints of near-memory computing well. On-chip measurements show the viability of both approaches with respect to memristor imperfections. The two Bayesian machines also operated well at low supply voltages. We also designed scaled-up versions of the machines. Both scaled-up designs can perform a gesture recognition task using orders of magnitude less energy than a microcontroller unit. We also see that if an accuracy lower than 86.9% is sufficient for this sample task, stochastic computing consumes less energy than logarithmic computing; for higher accuracies, logarithmic computation is more energy-efficient. These results highlight the potential of memristor-based near-memory Bayesian computing, providing both accuracy and energy efficiency.

This paper describes the design of a monolithic CMOS-memristive neuromorphic chip performing vector matrix multiplication between spike coded input vectors and the synaptic weights stored in the memristive array. A computing core including a$64\times 64$memristive array connecting 64 input and 64 output neurons has been fabricated. A Spiking Neural Network with a memristive synaptic layer exhibiting Stochastic Binary Spike-Time-Dependent-Plasticity has been experimentally demonstrated with the fabricated core. The CMOS-memristive neuromorphic processor is designed following a compact pseudo-CMOL design style that results in a modular and scalable computing core with a synaptic density of 22Ksynapses/mm2. A single core has been fabricated in CEA-LETI 130nm CMOS-RRAM technology and its operation has been experimentally characterized. A multicore architecture with reconfigurable connectivity, where cores can be interconnected to either share pre-synaptic neurons and expand post-synaptic neurons, or vice versa, share post-synaptic neurons and expand pre-synaptic neurons, is proposed and presented here.

Spiking Neural Networks (SNNs) can unleash the full power of analog Resistive Random Access Memories (RRAMs) based circuits for low power signal processing. Their inherent computational sparsity naturally results in energy efficiency benefits. The main challenge implementing robust SNNs is the intrinsic variability (heterogeneity) of both analog CMOS circuits and RRAM technology. In this work, we assessed the performance and variability of RRAM-based neuromorphic circuits that were designed and fabricated using a 130 nm technology node. Based on these results, we propose a Neuromorphic Hardware Calibrated (NHC) SNN, where the learning circuits are calibrated on the measured data. We show that by taking into account the measured heterogeneity characteristics in the off-chip learning phase, the NHC SNN self-corrects its hardware non-idealities and learns to solve benchmark tasks with high accuracy. This work demonstrates how to cope with the heterogeneity of neurons and synapses for increasing classification accuracy in temporal tasks.

Dedicated hardware implementations of spiking neural networks that combine the advantages of mixed-signal neuromorphic circuits with those of emerging memory technologies have the potential of enabling ultra-low power pervasive sensory processing. To endow these systems with additional flexibility and the ability to learn to solve specific tasks, it is important to develop appropriate on-chip learning mechanisms. Recently, a new class of three-factor spike-based learning rules have been proposed that can solve the temporal credit assignment problem and approximate the error back-propagation algorithm on complex tasks. However, the efficient implementation of these rules on hybrid CMOS/memristive architectures is still an open challenge. Here we present a new neuromorphic building block, called PCM-trace, which exploits the drift behavior of phase- change materials to implement long lasting eligibility traces, a critical ingredient of three-factor learning rules. We demonstrate how the proposed approach improves the area efficiency by > 10× compared to existing solutions and demonstrates a technologically plausible learning algorithm supported by experimental data from device measurements.

The design of systems implementing low precision neural networks with emerging memories such as resistive random access memory (RRAM) is a significant lead for reducing the energy consumption of artificial intelligence. To achieve maximum energy efficiency in such systems, logic and memory should be integrated as tightly as possible. In this work, we focus on the case of ternary neural networks, where synaptic weights assume ternary values. We propose a two-transistor/two-resistor memory architecture employing a precharge sense amplifier, where the weight value can be extracted in a single sense operation. Based on experimental measurements on a hybrid 130 nm CMOS/RRAM chip featuring this sense amplifier, we show that this technique is particularly appropriate at low supply voltage, and that it is resilient to process, voltage, and temperature variations. We characterize the bit error rate in our scheme. We show based on neural network simulation on the CIFAR-10 image recognition task that the use of ternary neural networks significantly increases neural network performance, with regards to binary ones, which are often preferred for inference hardware. We finally evidence that the neural network is immune to the type of bit errors observed in our scheme, which can therefore be used without error correction.

The advent of deep learning has considerably accelerated machine learning development. The deployment of deep neural networks at the edge is however limited by their high memory and energy consumption requirements. With new memory technology available, emerging Binarized Neural Networks (BNNs) are promising to reduce the energy impact of the forthcoming machine learning hardware generation, enabling machine learning on the edge devices and avoiding data transfer over the network. In this work, after presenting our implementation employing a hybrid CMOS - hafnium oxide resistive memory technology, we suggest strategies to apply BNNs to biomedical signals such as electrocardiography and electroencephalography, keeping accuracy level and reducing memory requirements. We investigate the memory-accuracy trade-off when binarizing whole network and binarizing solely the classifier part. We also discuss how these results translate to the edge-oriented Mobilenet V1 neural network on the Imagenet task. The final goal of this research is to enable smart autonomous healthcare devices.

Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage calibration scheme to calibrate the DC offset voltage across the rows of the memristive crossbar. The proposed method is based on biasing the body terminal of one of the differential pair MOSFETs of the buffer through a series of cascaded resistor banks arranged in three stages-coarse, fine and finer stages. The circuit is designed in a 130 nm CMOS technology, where the OxRAM-based binary memristors are built on top of it. A dedicated PCB and other auxiliary boards have been designed for testing the chip. Experimental results validate the presented approach, which is only limited by mismatch and electrical noise.

Many edge computing and IoT applications require adaptive and on-line learning architectures for fast and low-power processing of locally sensed signals. A promising class of architectures to solve this problem is that of in-memory computing ones, based on event-based hybrid memristive-CMOS devices. In this work, we present an example of such systems that supports always-on on-line learning. To overcome the problems of variability and limited resolution of ReRAM memristive devices used to store synaptic weights, we propose to use only their High Conductive State (HCS) and control their desired conductance by modulating their programming Compliance Current (ICC). We describe the spike-based learning CMOS circuits that are used to modulate the synaptic weights and demonstrate the relationship between the synaptic weight, the device conductance, and the ICCused to set its weight, with experimental measurements from a 4kb array of HfO2-based devices. To validate the approach and the circuits presented, we present circuit simulation results for a standard CMOS 180nm process and system-level behavioral simulations for classifying hand-written digits from the MNIST data-set with classification accuracy of 92.68% on the test set.

Brain-inspired architectures in neuromorphic hardware are currently subject to intensive research as an alternative to the limits of traditional computer organisation. The remarkable computing performance and efficiency of biological nervous systems are widely attributed to the co-localisation of memory and computation spatially throughout the structure. Moreover, it appears that a number of local self-organising neural mechanisms play their part in efficient biological computation. An example is neuronal intrinsic plasticity, where a neuron adapts its parameters to maximise its information capacity based on the statistical properties of its input while minimising the power it consumes. CMOS circuits implementing neuron models have been proposed but require their parameters to be set by biases originating from a centralised memory. In this work, we propose a hybrid CMOS-RRAM circuit that addresses this problem through storing neuron parameters within programmable nonvolatile resistive memories incorporated into the CMOS neuron. Additional circuits exploit the stochastic switching properties of resisitive memories to map a local intrinsic plasticity algorithm onto the proposed neuron. We demonstrate the computational advantages of this algorithm through simulation, calibrated on experimental data, whereby the neuron maximises its information capacity while minimising its power consumption, as is the case for biological neurons.

This paper presents a new current attenuator circuit to scale down the inference currents in memristor based crossbars that drive integrate-and-fire neurons, which subsequently allows to reduce the size of integrating capacitors by several orders of magnitude, making IC integration possible. The proposed circuit uses a linear switch to divide the inference current and scale it down by a factor of about 104. The proposed attenuator has been designed in 130nm CMOS technology. Simulation results considering noise, process and temperature variations are shown to validate the presented approach.

Neuromorphic computing is henceforth a major research field for both academic and industrial actors. As opposed to Von Neumann machines, brain-inspired processors aim at bringing closer the memory and the computational elements to efficiently evaluate machine learning algorithms. Recently, spiking neural networks, a generation of cognitive algorithms employing computational primitives mimicking neuron and synapse operational principles, have become an important part of deep learning. They are expected to improve the computational performance and efficiency of neural networks, but they are best suited for hardware able to support their temporal dynamics. In this survey, we present the state of the art of hardware implementations of spiking neural networks and the current trends in algorithm elaboration from model selection to training mechanisms. The scope of existing solutions is extensive; we thus present the general framework and study on a case-by-case basis the relevant particularities. We describe the strategies employed to leverage the characteristics of these event-driven algorithms at the hardware level and discuss their related advantages and challenges.

Resistive Random Access Memory (RRAM)-based artificial Neural Networks (NNs) have been shown to be intrinsically robust to RRAM variability but no study has been done to clearly explain and quantify this robustness. In this paper, we fully characterize a 4kbit RRAM array under different programming conditions. The impact of the electrical characteristics of RRAM (resistance variability, memory window, endurance performance) on the detection rate of a NN designed for object tracking and trained with a stochastic Spike-Timing Dependent Plasticity (STDP) rule is studied. We introduce a new parameter called the Synaptic Window (SW), defined as the ratio between the arithmetic mean conductance values of the low and high resistance distributions. The network performance was found only to be sensitive to the value of the SW (a SW>100 is required to achieve the maximum NN performance). Moreover, we demonstrate that a high resistance variability increases the SW for a given window margin.

This paper provides an overview of the challenges faced by hardware implemented Spiking Neural Networks, from device to circuit design, reliability and test. We present a comprehensive description of the state-of-the-art neuromorphic architectures inspired by brain computation, with special emphasis on Spiking Neural Networks (SNNs), together with emerging technologies that have enabled such systems, namely Phase Change and Metal Oxide Resistive Memories. Finally, we discuss the main challenges faced by hardware implementations of SNNs, their reliability and post-fabrication test issues.

Resistive random access memories (RRAMs) feature high-speed operations, low-power consumption, and nonvolatile retention, thus serving as a promising candidate for future memory applications. To explore the applications of the RRAM, switching variability and cycling endurance need to be addressed. This paper presents extensive characterizations of multi-kb RRAM arrays during forming, set, reset, and cycling operations. The relationships among programming conditions, memory window, and endurance features are presented. The experimental results are then used to perform variability-aware simulations of a 128-bit RRAM-based ternary content-addressable-memory (TCAM) macro. The tradeoff among endurance, search latency, and reliability in terms of match/mismatch detection is explored, identifying the programming conditions that allow to obtain a searching speed comparable to static random access memory-based TCAMs (2 ns on average and 3 ns at 3σ) while guaranteeing good reliability metrics (with a time ratio of 3000 on average and 150 at 3σ).

In this work, we will focus on the role that non-volatile resistive memory technologies (RRAM) can play for modeling key features of biological synapses. We will present an architecture and a reading/programming strategy to emulate both Short and Long Term Plasticity (STP, LTP) rules using non-volatile OxRAM arrays. A visual-pattern extraction application is discussed using spiking neural networks. We demonstrated that Long-Term plasticity allows the neural networks to learn patterns and the Short Term plasticity allows to improve accuracy (reduction of the false positive events generated by white noise in the input data) in presence of significant background noise in the input data.

This paper investigates the design architectures for reliable high-yield low operating voltage non-volatile flip-flops (NVFF) for zero-leakage and instantaneously-on ultra-low power applications in scaled CMOS technologies. A reliable thin-gate oxide NVFF, integrating OxRAM current-based storing and restoring solutions is designed and analyzed in 28nm FD-SOI. The proposed class of NVFF designs has been optimized for optimal OxRAM programming conditions that improve endurance and minimize programming power, while ensuring high yield. The OxRAM device silicon measurements show that a low programming current benefits endurance, but at the expense of a reduced memory window (ROFF/RON). Statistical analysis demonstrates that a low NVFF operating voltage in restore mode can be achieved with a narrow memory window by using the current-based restoring. In a representative design, compared to a standard FF, the non-volatility is added at the cost of less than 3% of performance and up to 3.5%-13% of active energy increase, with 108 cycles of endurance. Then compared with the data-retention FF supplied at 0.5V, NVFF reduces the sleep power consumption for standby modes longer than 0.34s for uniform Q switching (0.17s-0.6s) Finally, the low variability of the FD-SOI technology enables 3 sigma yield restore down to 0.7V.

An innovative approach for decoding of brain signals based on Spiking Neural Networks is presented in this paper. Synapses are implemented by BEOL compatible oxide resistive RAM (OxRAM) devices providing low programming voltages (<;2.5V) and currents (~30μA). Spike-timing-dependent plasticity enables the network for autonomous online spike sorting of measured biological signals. Ultra-low synaptic power consumption in the range of 10nW, recognition rates around 90% and real-time functionality bear high potential for future healthcare applications.

In this work, we will focus on the role that new nonvolatile resistive memory technologies can play in emerging fields of application, such as non-volatile logic circuits or neuromorphic circuits, to save energy and increase performance. Concerning the introduction of non-volatile functionalities at the logic level, we will demonstrate hybrid CMOS logic plus ReRAM (specifically CBRAM and OXRAM) circuits for ultra low power FPGA and fixed-logic IC design, as Non Volatile Flip-Flops. Concerning neuromorphic circuits, we will focus on the emulation of synaptic plasticity effects with resistive memory synapses. We will present large-scale energy efficient neuromorphic systems based on ReRAM as stochastic-binary synapses. Prototype applications such as complex visual- and auditory-pattern extraction will be also discussed using feedforward spiking neural networks.

Recent announcement of 16Gbits Resistive memory from Sony shows the trend to quickly adopt resistive memories as an alternative to DRAM. However, using ReRAM for embedded computing is still a futuristic goal. This paper approaches two applications based on ReRAM-devices for gaining area, performance or power consumption. The first application is FPGA, one of the first architecture that can benefit the most from ReRAM integration to reduce footprint and save energy. The second application relates to ultra-low-power systems and the way to obtain an instantaneous “freeze” mode in devices for Internet of Things.

At most advanced technology nodes, Field Programmable Gate Arrays (FPGA) present great advantages compared to more conventional processor architectures; their natural regularity, modularity and inherent reliability due to duplicated identical tiles provide a solution to overcome new technologies with increasing variability. However, FPGA market is still limited by power efficiency issue, due to two coordinated factors like interconnection-dominated design and large usage of memories, computation being performed thanks to Look-Up-Table (LUT). In this paper, we propose a solution to improve the performance and reduce the power consumption of LUT in FPGA using CBRAM-based structures. Our proposed design shows significant improvement compared to the traditional SRAM-based FPGA in: critical delay is reduced by ~23% due to compact structure (1T-2R) and power gain by reduction in static power consumption by ~18%.