Advanced cryptographic devices employ multiscale countermeasures to bolster resilience against side-channel analysis (SCA). In masking-based defenses, secure substitution-boxes (S-boxes) and effective masking schemes are paramount. Additionally, the time-based hiding techniques, leveraging multiple clocks for individual encryption operations, offer significant protection. This article introduces a novel multiscale countermeasure: an improved tower field masking scheme integrated with an affine transformation-based dynamic S-box. Crucially, we incorporate Gold sequences to generate both a random clock source for horizontal hiding and random values for masking. Extensive evaluation using up to five million power traces demonstrates the robustness of our approach against standard correlation power analysis (CPA) and alignment preprocessing techniques, including sliding window and amplitude peak localization. Experimental results show a measurement-to-disclosure (MTD) improvement of at least$150\times $compared to unprotected implementations using stand-alone masking and$375\times $with our multiscale approach. Furthermore, we demonstrate resilience against recent robust profiled deep learning SCA, which could only recover four subkeys even with one million traces.

Digital and all-digital resonate-and-fire (RAF) neurons are the newest models for researching spiking neurons and spiking neuron networks (SNN). They are usually researched and developed using time-driven simulation. This type of simulation usually requires powerful computer systems, especially in training networks. Moreover, the digital and all-digital RAF neurons have two cases of firing, leading to hard training for these kinds of neurons compared to leaky integrate-and-fire (LIF) neurons. This research suggested a probability method to find out the firing probability without running a time-driven simulation. By doing so, the research proposed a method to calculate the eigenperiod and pulse width of these types of RAF neurons for machine learning applications.

The Mixed-Mode Clock Manager (MMCM) is a primitive in Xilinx FPGAs that is designed for generating a wide range of output clock frequencies by utilizing a fixed input clock signal. It has been applied to numerous cryptographic devices to improve their side-channel attack resistance. This paper proposes an efficient hiding countermeasure by using the MMCM in spread spectrum mode. In our suggested architecture, the hardware implementation is given by random dynamic frequency-hopping signals. We could achieve better effectiveness in the occupied bandwidth metrics and found 223 available parameter sets, which is significantly smaller than using 219k distinct sets in a previous study, namely a random dynamic frequency scaling countermeasure. The experimental results indicate that a recent deep learning-based leakage assessment requires nearly one million traces to detect leakage points, whereas the well-known t-test methodology cannot detect any information leakage in five million measurements. Furthermore, this countermeasure is capable of withstanding both conventional and sliding window-based Correlation Power Analysis attacks, despite utilizing up to five million power traces.

Side-channel analysis attacks have become the primary method for exploiting the vulnerabilities of cryptographic devices. Therefore, focusing on countermeasures to enhance the security level of these implementations evolves even more urgently. This article proposes a time-based hiding countermeasure by using spread-spectrum signals. In our RISC-V system on chip (SoC), cryptographic accelerators are given by random dynamic frequency-hopping signals. We found 223 available parameter sets for a Xilinx Mixed-Mode Clock Manage primitive in spread spectrum mode and achieved better effectiveness in the occupied bandwidth (OBW) metric. The mixed mode clock managers (MMCMs) output signal and the range of frequencies within the spread will be changed randomly, resulting in multiple clocks for individual encryption. The effectiveness of this proposal is demonstrated by conducting realistic side-channel attacks (SCAs) and state-of-the-art leakage assessment methodologies on the well-known data encryption standard, i.e., the Advanced Encryption Standard (AES) accelerator. Even though we used up to five million power traces, the test results show that our defense can stand up to a regular correlation power analysis (CPA) attack as well as alignment preprocessing methods, like CPA attacks that use a sliding window or an amplitude peak location algorithm. Furthermore, the t-test methodology cannot detect any first-order information leakage in five million traces; meanwhile, the deep learning leakage assessment (DLLA) requires nearly one million power traces in the training test to detect leakage points.

In this demonstration, a real-time auto-exposure Histogram Equalization (HE) video-system is presented. The video histogram is extracted in each frame by the Frequent Items Counter (FIC) core. Based on the HE Transformation Function (HE-TF), the camera exposure value is adjusted to fit the current luminance condition. The proposed system was developed on the VEEK-MT-SoCKit with an FPGA chip of Altera Cyclone V SoC and a 5-Megapixel (5-MP) Charge Coupled Device (CCD). The video resolution is 1280×800. The monitor display rate is at 60Hz while the CCD capture rate is at 24.28Hz to 38.98Hz depend on the exposure value. The histogram, the transformation function, and the camera exposure value are changed in each frame to satisfy the real-time requirement.

In this paper, the high-speed Discrete Cosine Transform (DCT) architecture is presented using the Adaptive CORDIC (ACor) algorithm built with a fixed-rotation angle. The proposed method is implemented in six different versions corresponding to the number of DCT point, i.e., 8-point (8p), 16-point (16p), and 32-point (32p), and the number of ACor stages, i.e., 2-Stage (2S) and 3-Stage (3S). The implementations are built and verified on an Altera Stratix IV FPGA. The 2S designs of 8p-DCT, 16p-DCT, and 32p-DCT achieve the maximum operating frequencies of 179.86 MHz, 162.60 MHz, and 136.97 MHz, respectively. Moreover, the 2S-32p-DCT module is implemented in ASIC with the 65nm-SOTB CMOS technology. The synthesis shows that the core costs 47.2K gates and consumes about 0.68 mW while operating at 100 MHz clock rate. The 2S implementations of 8p-DCT, 16p-DCT, and 32p-DCT achieve four, five, and six adder-delay, mean-square-error of 1.403e-4, 2.029e-2, and 7.663e-2, and coding gain of 8.8108 dB, 9.0984 dB, and 9.2170 dB, respectively. In comparison with recent works, the proposed method achieves the best timing performances, good accuracy results, and adequate resources cost.

In this paper, a hybird adaptive Coordinate Rotation Digital Computer (HA-CORDIC) has implemented in 65nm Silicon On Thin Buried oxide (SOTB) CMOS technology. In the HA-CORDIC implementation, the adaptive algorithm is utilized for reducing the iteration of CORDIC algorithm. In comparison with other floating-point CORDIC designs, the latency of our proposed scheme is lower. It spends only 12, 20, and 26 clocks cycles in the best, average, and worst case, respectively. The HA-CORDIC exploits some design techniques such as resource sharing, pipeline, and parallel processing to achieve low-resource and low-latency. In 65nm SOTB CMOS technology, this design is able to operate at 50 MHz frequency with 0.5 V supply voltage, 0.36 mA current, and 0.058 mm2 area. Its power consumption of HA-CORDIC is 0.251 mW, about three times lower than the one in conventional CMOS technology. Its leakage current is about 0.492 μA if the supply voltage VDD is 0.4 V and the bias voltage VBB is -1.5 V. This leakage current is about four times lower than that of HA-CORDIC implementing in conventional CMOS.

This article introduces a dynamic cloud-based marketplace of near-realtime human sensing data (MARSA) for different stakeholders to sell and buy near-realtime data. MARSA is designed for environments where information technology (IT) infrastructures are not well developed but the need to gather and sell near-realtime data is great. To this end, we present techniques for selecting data types and managing data contracts based on different cost models, quality of data, and data rights. We design our MARSA platform by leveraging different data transferring solutions to enable an open and scalable communication mechanism between sellers (data providers) and buyers (data consumers). To evaluate MARSA, we carry out several experiments with the near-realtime transportation data provided by people in Ho Chi Minh City, Vietnam, and simulated scenarios in multicloud environments.

Developing and operating IoT cloud systems require novel features for deploying, controlling, monitoring and testing both IoT units and cloud services in an integrated environment spanning different infrastructures. In this paper, we demonstrate iCOMOT -- a novel toolset offering these features. Using iCOMOT we can perform various activities, such as dynamically reconfiguration of sensors, communication protocols, and cloud services in an elastic manner, suitable for testing and assuring quality of IoT cloud systems configurations. We will demonstrate our iCOMOT with a real-world predictive maintenance case study.

Contemporary cloud services are constructed from different types of software and deployed on multiple cloud infrastructures, which offer various configuration options, and can change dynamically at runtime. Due to this complexity, such cloud services require substantial configuration efforts. Currently we lack techniques for automating the complex tasks and providing fine-grained configuration features for multi-cloud services. In this paper, we present a novel multi-level configuration approach for complex cloud services on multi-cloud environments. We develop techniques for automating configuration orchestration activities. Our solution enables the fine-grained configuration at different application abstraction levels and supports the dynamic change of cloud services at runtime. We provide the SALSA framework to implement our approach and demonstrate its usefulness with several real-world services.

Platform-as-a-Service (PaaS) should support the design, deployment, execution, test and monitoring of native elastic systems constructed from elastic service units based on multi-dimensional elasticity requirements. In this paper, we discuss fundamental building blocks for enabling multi-dimensional elasticity programming of software-defined elastic systems. We describe CoMoT, a novel PaaS for elasticity in the cloud that is developed based on these fundamental building blocks.

A CAM-based (Content Addressable Memory) image matching system is implemented on hardware system using FPGA. The system has simple structure, does not employ any Central Processor Units (CPUs) as well as complicated computations. The authors take advantages of CAM which has an ability of parallel multi-match mode for designing the system. Thus increases the matching performance of the system. The system is applied for exact image matching or approximate image matching with various required search patterns without using search principles. In this paper, the authors present the system for fast image matching applications on 2-D data.