Deep learning models offer state-of-the-art performance but their inherent opacity is a major barrier to adoption in high-stakes domains. In contrast, Takagi-Sugeno-Kang (TSK) fuzzy systems provide rule-based transparency but often lack the predictive power of deep networks. My PhD research addresses this critical trade-off by developing the Fuzzy-Modulated Linear Consequents (FMLC) framework, a novel hybrid architecture that synergizes these two paradigms. The core of FMLC is a deep neural network that processes fuzzified input features to generate context-dependent "modulators". These modulators dynamically parameterize a TSK-style linear consequent layer, creating a model that is both highly performant and inherently interpretable. My latest work, Learnable-FMLC (L-FMLC), advances this by introducing a regularized, adaptive fuzzification layer that autonomously learns the optimal fuzzy partitions from data, and a two-stage rule distillation framework to ensure interpretability remains scalable in high-dimensional problems. This research delivers a validated, theoretically-grounded, and scalable framework, contributing a significant step towards transparent and trustworthy AI.

The stress of verifying and validating nowadays complex systems is continuously boosting. To address this imperative issue, we present an optimised assertion checking approach that dynamically implements an instruction-based checker to validate system properties during run-time. In contrast to state-of-the-art hardware checker, the presented method compiles an assertion to a microprogram, which can be changed very flexibly by software for the in-silicon validation. A stand-alone hardware block, named assertion checking unit (ACU), is designed for executing the compiled microprogram in real-time. We have successfully evaluated this approach to detect run-time error of a prototyped cryptographic system by means of a run-time fault injection technology. Additionally, we have achieved measurable benefits of the new approach compared to the previous work.

Recently, Assertion-Based Verification (ABV) has been significantly improved and used not only in academia but also in industry. In this paper, we present a new assertion checking approach that dynamically interprets a software-defined assertion checker during run-time. In contrast to the state-of-the-art hardware checker, the presented method compiles its checker to instructions, which can be changed flexibly by software in the in-silicon phase. A stand-alone hardware block, called assertion processing unit (APU), is used for implementing the compiled instructions. This unit handles the storage of the checker code, the execution of the checking, and the feedback of checked results in the system run-time environment. We have successfully evaluated this approach on an FPGA-based prototyping board, showing measurable benefits of this approach.