Optical deep learning (DL) accelerators have attracted significant interests due to their latency and power advantages. In this article, we focus on incoherent optical designs. A significant challenge is that there is no known solution to perform single-wavelength accumulation (a key operation required for DL workloads) using incoherent optical signals efficiently. Therefore, we devise a hybrid approach, where accumulation is done in the electrical domain, and multiplication is performed in the optical domain. The key technology enabler of our design is the transistor laser, which performs electrical-to-optical and optical-to-electrical conversions efficiently. Through detailed design and evaluation of our design, along with a comprehensive benchmarking study against state-of-the-art RRAM-based designs, we derive the following key results: (1) For a four-layer multilayer perceptron network, our design achieves 115× and 17.11× improvements in latency and energy, respectively, compared to the RRAM-based design. We can take full advantage of the speed and energy benefits of the optical technology because the inference task can be entirely mapped onto our design. (2) For a complex workload (Resnet50), weight reprogramming is needed, and intermediate results need to be stored/re-fetched to/from memories. In this case, for the same area, our design still outperforms the RRAM-based design by 15.92× in inference latency, and 8.99× in energy.

We present a hybrid optical-electrical analog deep learning (DL) accelerator, the first work to use incoherent optical signals for DL workloads. Incoherent optical designs are more attractive than coherent ones as the former can be more easily realized in practice. However, a significant challenge in analog DL accelerators, where multiply-accumulate operations are dominant, is that there is no known solution to perform accumulation using incoherent optical signals. We overcome this challenge by devising a hybrid approach: accumulation is done in the electrical domain, while multiplication is performed in the optical domain. The key technology enabler of our design is the transistor laser, which performs electrical-to-optical and optical-to-electrical conversions efficiently to tightly integrate electrical and optical devices into compact circuits. As such, our design fully realizes the ultra high-speed and high-energy-efficiency advantages of analog and optical computing. Our evaluation results using the MNIST benchmark show that our design achieves 2214× and 65× improvements in latency and energy, respectively, compared to a state-of-the-art memristor-based analog design.

We present the first all-optical network, Baldur, to enable power-efficient and high-speed communications in future exascale computing systems. The essence of Baldur is its ability to perform packet routing on-the-fly in the optical domain using an emerging technology called the transistor laser (TL), which presents interesting opportunities and challenges at the system level. Optical packet switching readily eliminates many inefficiencies associated with the crossings between optical and electrical domains. However, TL gates consume high power at the current technology node, which makes TL-based buffering and optical clock recovery impractical. Consequently, we must adopt novel (bufferless and clock-less) architecture and design approaches that are substantially different from those used in current networks. At the architecture level, we support a bufferless design by turning to techniques that have fallen out of favor for current networks. Baldur uses a low-radix, multi-stage network with a simple routing algorithm that drops packets to handle congestion, and we further incorporate path multiplicity and randomness to minimize packet drops. This design also minimizes the number of TL gates needed in each switch. At the logic design level, a non-conventional, length-based data encoding scheme is used to eliminate the need for clock recovery. We thoroughly validate and evaluate Baldur using a circuit simulator and a network simulator. Our results show that Baldur achieves up to 3,000X lower average latency while consuming 3.2X-26.4X less power than various state-of-the art networks under a wide variety of traffic patterns and real workloads, for the scale of 1,024 server nodes. Baldur is also highly scalable, since its power per node stays relatively constant as we increase the network size to over 1 million server nodes, which corresponds to 14.6X-31.0X power improvements compared to state-of-the-art networks at this scale.

The articles in this special issue focus on the history and development of light emitting diode (LED) technology and industry applications over the last fifty years.

The quantum-well (QW) heterojunction bipolar transistor (HBT) laser [the transistor laser (TL)], inherently a fast switching device, operates by transporting small minority base charge densities$\sim\!\! {\hbox {10}}^{16}\ {\hbox {cm}}^{-3}$over nanoscale base thickness ($<$900 A) in picoseconds. The base QW acts as an optical “collector,” in addition to the usual electrical collector, that selects out “fast” recombining carriers, resulting in a short lifetime ($\sim$29 ps) and higher differential laser gains. Charge and current continuity, together with the boundary conditions imposed by both collectors of the TL lead to a new charge control model, “unpinning” of population inversion beyond lasing threshold, quasi-Fermi level discontinuity across base QW, and a new equivalent circuit model requiring an extension to Kirchhoff's law. With the TL, the HBT becomes more than just a charge control device, but also a photon storage and switching device. The TL, owing to fast recombination speed, its unique three-terminal configuration, and the complementary nature of its optical and electrical collector output signals, enables resonance-free base current and collector voltage modulations, and compact realization of electro–optical applications such as nonlinear signal mixing, frequency multiplication, negative feedback, and optoelectronic logic gates.

Next-generation high data rate wireless communication systems offer completely new ways to access information and services. To provide higher data speed and data bandwidth, RF transceivers in next-generation communications are expected to offer higher RF performance in both transmitting and receiving circuitry to meet quality of service. The semiconductor device technologies chosen will depend greatly on the tradeoffs between manufacturing cost and circuit performance requirements, as well as on variations in system architecture. It is hard to find a single semiconductor device technology that offers a total solution to RF transceiver building blocks in terms of system-on-chip integration. The choices of device technologies for each constituent component are important and complicated issues. We review the general performance requirement of key components for RF transceivers for next-generation wireless communications. State-of-the-art high-speed transistor technologies are presented to assess the capabilities and limitations of each technology in the arena of high data rate wireless communications. The pros and cons of each technology are presented and the feasible semiconductor device technologies for next-generation RF transceivers can be chosen upon the discretion of system integrators.

The area and power consumption of oversampling analog-to-digital converters (ADCs) are governed largely by the associated digital decimation filter. This paper presents a low power, area-efficient digital decimation filter for an oversampling ADC application that employs the decorrelating (DECOR) transform in order to reduce the power dissipation and area. The DECOR transform exploits the correlation in the coefficients and data sequences to reduce the precision. Simulation results indicate that a decorrelated 8192-tap decimation filter with a decimation ratio of 64 results in a reduction of 5 bits in the coefficient and accumulator size. This corresponds to savings in complexity of 25%. In multi-stage decimation filters, it is shown that the decimation ratio of the last stage needs to be greater than 4 for DECOR to be useful.

This paper presents several novel approaches to improve the dynamic performance of a high-speed, high-resolution digital-to-analog converter (DAC). In order to improve the resolution of a 14-bit DAC, a double segmented decoding plus R-2R architecture is introduced. DAC system modeling shows that the dynamic performance of the DAC is strongly dependent on the output impedance of DAC current sources. The gain-boosting technique is applied to increase the output impedance of DAC current sources. A novel switch driver is introduced to further improve dynamic performance by isolating digital switching noise from the analog output. Multiple-level emitter coupled logic (MEL) is applied to the decoder logic due to its superior propagation time over emitter-coupled logic (ECL). The DAC circuit was designed using a 60 GHz f/sub T/ InGaP-GaAs HBT process. From circuit simulation, we find 0.62 LSB differential non-linearity (DNL), 0.71 LSB integral non-linearity (INL) and 1.25 ns settling time.

The track-and-hold amplifier (THA) is a key sub-circuit in a data acquisition and conversion system. The input buffer of the THA employs an open-loop linearization technique to reduce distortion and increase bandwidth. The hold mode feedthrough is reduced by the replica switch technique. The parasitic capacitance compensation technique is employed to further improve the signal bandwidth of the THA. Simulation results indicate that the parasitic capacitance compensation technique improves the bandwidth by approximately a factor of 5. The THA circuit was designed using a 60 GHz f/sub T/ InGaP-GaAs HBT process. Simulation results are 83 dB spurious-free dynamic range (SFDR) at 100 MHz sampling frequency, 65 dB SFDR at 1 GHz sampling frequency, and 60 dB SFDR at 2 GHz sampling frequency under all Nyquist conditions.

The long-range vision of the Engineering Research Center for Compound Semiconductor Microelectronics (CCSM) is focused on a new generation of high-speed communications and data-processing technology which exploits the bandwidth, immunity to electromagnetic interference, and connectivity of optical interconnects. In order to realize this vision, it will be necessary to design, fabricate, and integrate high-performance electrical and optical devices in monolithic optoelectronic integrated circuits, OEIC's. The research programs of the CCSM are focused on the development of the engineering science and technology base for fabrication of OEIC's and their application in optical interconnect systems; the education of engineers in this field; and effective transfer of this technology to industry