This paper reports an ultra-low voltage (ULV) relaxation oscillator (RxO) suitable for self-powered devices, designed with a pair of asymmetric swing-boosted (ASB) RC networks. This work enhances low-voltage operational capabilities and improves frequency stability and jitter performance. The RxO features a unique single amplifier configuration incorporated with a customized feedback mechanism that effectively compares the output voltages from the RC networks, substantially reducing jitter due to flicker noise. Additionally, we implement a Duty-Cycling Circuit (DCC) based on a DLL architecture to turn on the amplifier before the desired detection point, providing ample guard time and thereby reducing power consumption, which is essential for ultra-low power applications. The RxO also features a Replica Temperature Compensation Circuit (RTCC) to mitigate circuit delay. Fabricated in 65-nm CMOS, the RxO operates at 2.35 MHz with a minimal supply voltage of 0.5 V, achieving a period jitter of 390 ppm and line sensitivity of 17.4%, and an energy efficiency of 5.82 pJ/cycle. The device demonstrates significant improvements over existing ULV designs, achieving up to 60% reduction in power consumption while maintaining lower jitter levels.

This article presents a fully integrated CMOS rectifier with dual-band (0.9/1.8 GHz) harvesting capability and wide input power ($P_{\mathbf {IN}}$) operational range, targeting on-chip ambient RF energy harvesting (AREFH) applications. The proposed work enhances the performance by addressing two primary PCE’s dynamic range (PDR) limiting loss mechanisms: reverse current loss ($P_{\mathbf {LO-REV}}$) and impedance mismatch reflection loss ($P_{\mathbf {LO-REFL}}$).$P_{\mathbf {LO-REV}}$is mitigated using a six-/nine-stage extension technique. At the same time,$P_{\mathbf {LO-REFL}}$is reduced through a fully integrated dual-domain impedance matching network (IMN) employing series and shunt resonant techniques. Implemented in 65-nm CMOS, the proposed prototype occupies an active area of 0.23 mm${}^{\mathbf {^{2}}}$and was experimentally validated via on-wafer probing. Measurement results demonstrate the peak power conversion efficiency (PCE) of 43.6% at 0.9 GHz and 47.1% at 1.8 GHz under a 100-k$\Omega $load. Moreover, the proposed rectifier achieves a 15-dB PDR at both harvesting frequencies, representing the widest PDR among prior single-band and multiband fully on-chip works, thereby highlighting its competitiveness for practical ARFEH applications.

In this paper, we present a fully integrated dual-dimensional reconfigurable charge pump (DDR-CP) for energy harvesting (EH) applications. EH systems often encounter significant input voltage variations due to changing environmental conditions, posing a challenge for conventional CPs, which are efficient only at discrete input-to-output voltage ratios. This limitation restricts their performance and efficiency over a wide power dynamic range (PDR). To address this, the proposed DDR-CP incorporates a dual-dimensional reconfiguration approach, optimizing operating frequency and CP stage configuration to maximize system efficiency across varying input and load conditions. A novel frequency tuning mechanism,termeddynamic source feed, is devised. Also, a mathematical analysis of dominant power losses over a wide PDR is derived, providing a robust design guideline for CP optimization. Fabricated in a 65-nm CMOS process, our DDR-CP integrates a total on-chip pumping capacitor of 176 pF within a compact active area of 0.286 mm2. The DDR-CP supports tri-mode operation, handling input voltages from 0.21 V to 0.7 V, and delivers up to$40~\mu $W of output power. Measurement results demonstrate a peak PCE of 73% and an average PCE ranging from 30% to 70% across the entire input range, validated under a 55-K$\Omega $output load.

This brief presents an output-capacitorless low-dropout (OCL-LDO) regulator based on flipped-voltage-follower (FVF) and dual pMOS pass transistors. An adaptive-compensation buffer (ACB) dynamically regulates the operation of the pass transistors. Specifically, when the load current falls below 5 mA, only the smaller pass transistor is activated; otherwise, both pass transistors are engaged, thereby simultaneously mitigating the minimum load current requirement for FVF architecture and extending the load current ranging from 0 to 30 mA while maintaining stability without an external load capacitor. At 1.15-V supply voltage and 0-mA load current, the quiescent current is$6~\mu $A. The output voltage is 1.0 V with a dropout voltage of 0.15 V. Measurements show that with a load current stepping from 0 to 30 mA at an edge time of 100 ns, the output voltage undershoot is 0.2 V with a recovery time of 200 ns while achieving a load regulation of 0.23 mV/V. Our OCL-LDO is fabricated in a 180-nm CMOS with an active area of 0.031 mm2.

This article presents a fully integrated tri-band RF energy harvesting system (RFEH) in 65-nm CMOS technology. The system is designed to harvest ambient RF energies at 900 MHz, 1.9 GHz, and 2.4 GHz through a tri-band impedance matching network (IMN), cross-coupled differential-drive (CCDD) rectifier, and an output voltage monitoring circuit to limit the rectified output voltage to 3.3 V. The system achieves a power conversion efficiency (PCE) of over 30 % across all three frequency bands with a peak of 42.8 %. Furthermore, the system exhibits a peak sensitivity of -20 dBm at an output DC voltage of 1$V$output.

This brief reports a dual-topology CMOS rectifier with an extended power dynamic range (PDR) for radio frequency (RF)-based hybrid energy harvesting (RF-HEH) systems. By leveraging both the cross-coupled differential drive (CCDD) and the Dickson topologies with high forward conduction and low reverse leakage, we obtain an extension of the rectifier’s PDR by adaptively disabling the CCDD counterpart and enabling the Dickson counterpart to dominate the rectifier’s performance during high-power operation. Apart from that, we formulate a rectifier-performance index (RPI), which accounts for the power conversion efficiency (PCE), the PDR, the sensitivity, and the load resistance of the rectifier to provide an adequate performance benchmark with the state-of-the-art rectifiers. Fabricated in a 130-nm CMOS, the proposed dual-topology rectifier measures a wide PDR of 19.5 dB with a peak PCE of 78.4% for a 100-$\text{k}\Omega $load operating at 900 MHz. Besides, our prototype records the highest RPI of 19.2 compared to the recent arts operating at GSM900.

This brief proposes a 900-MHz novel CMOS-reconfigurable stack rectifier (RSR) implemented in a three-stage cross-coupled differential rectifier (CCDR) for battery-assist Internet-of-Things (IoT)/wireless sensor network (WSN) applications. A three-mode RSR is incorporated for an extended dynamic range (DR) input power level with a 100-$\text{k}\Omega $load, fabricated in the 130-nm CMOS. The realized RSR achieves a wide DR power conversion efficiency (PCE) by reducing the ON-resistance (${R} _{\mathrm{\scriptscriptstyle ON}}$) in the low-power zone (LPZ) achieved by reducing the threshold voltage (${V} _{\text {th}}$) of the device and alternately increasing${V} _{\text {th}}$in the high-power zone (HPZ) by implementing the proposed reconfigurable stack transistor technique along with the multithreshold voltage (MTV) technique. The circuit observes a measured result of 47.91% in peak PCE at an input power of −14 dBm by driving a 100-$\text{k}\Omega $load. The proposed circuit also achieved 22.8 and 16.3 dB of DR with a PCE over 20% and 30%, respectively. Compared to other state-of-the-art designs, our work exhibits better DR and PCE.

Welcome to the Special Issue Based on the 17th Edition of the Asia Pacific Conference on Circuits and Systems.

This brief presents a novel circuit architecture for a Dickson-based reconfigurable rectifier with wide power dynamic range (PDR). Besides, a novel figure of merit (FoM) concerning the reconfigurable rectifiers is formulated to provide a more comprehensive assessment of the rectifier’s performance. The proposed reconfigurable design improves the operating range of the rectifier by adaptively switching between the six-stage configuration during low-power operation and the 12-stage configuration during high-power operation. Fabricated in 130-nm CMOS, the proposed reconfigurable rectifier measures a PDR of 14 dB with a peak power conversion efficiency (PCE) of 34.93% for 1-$\text{M}\Omega $load operating at 900 MHz. Relative to the recently published reconfigurable rectifiers, our design records the highest FoM of 36.98 dB/mm2, with minimum harvesting downtime.

This article describes a fully integrated CMOS radio frequency energy-harvesting (RFEH) front end. It features an on-chip stacked step-up transformer integrated with a cross-coupled differential drive (CCDD) rectifier to enhance the input sensitivity. The transformer also serves as an on-chip balun for the CCDD rectifier. The CCDD rectifier innovates a gate-biasing technique and realizes coupling capacitors at the end of each stage to increase the subsequent stage biasing. Here, our RFEH front end operating at 900 MHz achieves an improved sensitivity of −20 and −19.2 dBm at the 1-V output for no-load and a 1-$\text{M}\Omega $load, respectively.

This article proposes two linearization techniques in improving the third-order input intercept point (IIP3) of a balun-low-noise amplifier (LNA) mixer. First, the intrinsic third-order intermodulation (IM3) product of the inductively source degenerated (ISD) transconductor from the second-order derivative transconductance component (g"m) is reduced by tailoring toward the optimum biasing point at the moderate-inversion region. Second, the generated IM3 current by the first-order derivative transconductance (g'm) due to the interaction with the feedback component in the ISD transconductor is attenuated by second-harmonic injection via the bulk of the ISD transconductor. Furthermore, a transformer-based gate inductor and a transformer-based balun are applied to improve the input impedance matching and produce a balanced differential input signal. Measured results in 0.13-μm CMOS show a high IIP3 of +16 dBm and a conversion gain (CG) of 22 dB at 2.4 GHz. The double-sideband (DSB) noise figure (NF) is 7.2 dB, and the power consumption is 3.15 mW at 1.2 V.

This article reports a novel differential-folded mixer with multiple-feedback techniques for performance enhancement. Specifically, we introduce the capacitor cross-coupled (CCC) common-gate (CG) transconductance stage to improve the noise figure (NF) at low power by boosting the effective transconductance, while enhancing the linearity via suppressing the second-order harmonic distortion. Typically, the created loop gain of the CCC can raise the third-order intermodulation (IM3) distortion, penalizing the input-referred third-order intercept point (IIP3). Here, we propose a positive and a second capacitive feedback into the CCC CG transconductor, not only to suppress the IM3 distortion current but also adds in design flexibility to the input transistors. Furthermore, the positive feedback also improves the input impedance matching, conversion gain, and NF through a flexible design criterion. Prototyped in a 0.13-μm process, the proposed mixer operating at 900 MHz dissipates 4 mW at 1 V. The measured double sideband (DSB) NF is 8.5 dB, the conversion gain (GC) is 18.4 dB and the IIP3 is +12.5 dBm.

This paper proposes a dual-layer patterned floating shield (DL-PFS) technique for Silicon-based on-chip spiral inductors. By optimally utilizing the two lowest metal layer strips to shield the inductor from the substrate, electromagnetic (EM) simulations show 40% improvement of the Q factor when compared with the conventional approach. Designed and simulated in 0.13-μm CMOS, the DL-PFS inductor in a class-B VCO achieves 6.6-dB lower phase noise, and 34% power savings. The VCO also exhibits 9.7-to-10.93 GHz tunability, and -123-dBc/Hz phase noise at a 3 MHz offset. The power consumption is 1.64 mW at 0.6 V, leading to a state-of-the-art FoM of 190.5 dBc/Hz.