Huan-Hua Huang

dblp:123/5688 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware reliability and fault tolerance · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
fault masking
0.212013
Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Hardware reliability and fault tolerance
memory reliability
0.212013
Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Hardware reliability and fault tolerance › memory repair
built-in self-repair
0.012013
Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013

Methods — techniques the papers use, named apart from their topics

fault replacement · 0.2fault masking · 0.2
YearPublicationVenuePosition
2013 Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs
abstract
Single isolated fault (SIF) stands for about 60%-70% of the total number of defects and is rather redundancy hungry since a spare row or a column is required for repairing each SIF. Therefore, manufacturing yield will decrease if we do not allocate sufficient spare resources. In this paper, instead of the traditional fault replacement techniques, synergistic techniques that integrate both fault replacement and fault masking techniques are proposed. With our approaches, SIFs are masked instead of the traditional replacement for repairing. For other minor fault types (e.g., faulty rows and faulty columns), the fault replacement technique is used as usual. According to simulation results, repair rates can be improved significantly. The proposed techniques can be integrated with the conventional built-in self-repair with nearly negligible hardware overhead.
Shyue-Kung Lu, Huan-Hua Huang, Jiun-Lang Huang, Pony Ning
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2