Modern power grids use via arrays to connect wires across metal layers. These arrays are susceptible to electromigration (EM), which creates voids under the vias, potentially causing circuit malfunction. We combine the effect of via redundancy with models that characterize the effect of via array geometry on thermomechanical stress, and determine how the choice of via arrays can affect EM-induced failure in a power grid based on IR-drop threshold based failure criteria.

Electromigration (EM) is a growing concern in on-chip interconnects, particularly in the computing and automotive domains. EM can cause wire resistances in a circuit to increase, which may result in circuit performance failure within the lifetime of a product. Classical circuit-level EM models have two drawbacks: first, they do not accurately capture the physics of degradation in modern copper dual-damascene (Cu DD) metallization and second, they fail to model the inherent resilience in a circuit that may allow it to continue to function even after some wires fail. This paper overcomes both limitations, and develops a method to analyze the effect of EM on the resistance of wires in a circuit. For a single wire, our probabilistic analysis encapsulates known realities about Cu DD wires, e.g., that some regions of these wires are more susceptible to EM than others, and that void evolution shows statistical behavior. We develop a new criterion for identifying mortal wires based on this analysis. One part of the criterion incorporates the achievement of steady state and provides a result that is slightly tighter than the traditional Blech criterion, while another part is tied to the lifetime of the system. We apply these ideas to the analysis of on-chip power grids and demonstrate the inherent robustness of these grids that maintains supply integrity under some EM failures.

A fast and stochastic analysis methodology for electromigration (EM) assessment of power distribution networks is presented in this paper. We examine the impact of variability on EM time-to-failure (TTF), considering altered current densities due to global/local process variations as well as the fundamental factors that cause the conventional EM TTF distribution. Through the novel variations-aware current density model based on Hermite polynomial chaos, we demonstrate significant margins in EM lifetime when compared with the traditional worst case approach. On the other hand, we show that the traditional approach is altogether incompetent in handling transistor-level local variations leading to significantly optimistic lifetime estimates for lower metal level interconnects of power delivery network. Subsequently, we attempt to bridge the conventional, component-level EM verification method to the system level failures, inspired by the extreme order statistics. We make use of asymptotic order models to determine the TTF for the kth component failure due to EM, and demonstrate application of this approach in developing IR drop aware system-level failure criteria.

Today's methodologies for electromigration (EM) identify EM-susceptible wires based on their current density, using the Blech criterion to filter out wires that are EM-immortal. The Blech criterion is agnostic to the product lifetime and temperature conditions: many Blech-mortal wires may never experience EM during the product lifetime. We develop new methods that evaluate the transient evolution of stress, relative to the product lifetime, and present an improved set of simple and practical mortality criteria. On a set of power grid benchmarks, we demonstrate that the actual number of mortal wires may depend strongly on the lifetime and reliability conditions.

Over the years, there has been tremendous progress in developing new methods for modeling and diagnosing reliability at the level of individual transistors and interconnects. The thrust to propagate these models to higher levels of abstraction to predict the reliability of larger circuits is much more recent. This paper addresses the intersection of physics, circuits, and architecture for reliability modeling and optimization that must come together for cross-layer optimization. For various device reliability phenomena, this paper shows how physical models can be leveraged at the circuit level, or circuit models at the architecture level, to deliver composite solutions that comprehend chip-level design goals.

Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mechanism in nanometer-scale technologies. This paper addresses the problem of EM on signal interconnects and on Vdd and Vss rails within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects. We also present a graph-based algorithm that computes the currents when the pin position is moved avoiding a new characterization for each pin position and consequently considerably reducing the characterization time. We use the cell lifetime analysis to determine the lifetime of large benchmark circuits, and show that these circuit lifetimes can be improved by about 2.5×-161× by avoiding the EM-critical output, Vdd, and Vss pin positions of the cells, using minor layout modifications.

Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. This work addresses the problem of EM on signal interconnects within a standard cell. An approach for modeling and efficient characterization of cell-internal EM is developed, incorporating Joule heating effects, and is used to analyze the lifetime of large benchmark circuits. Further, a method for optimizing the circuit lifetime using minor layout modifications is proposed.

Electromigration (EM), a growing problem in on-chip interconnects, can cause wire resistances in a circuit to increase under stress, to the point of creating open circuits. Classical circuit-level EM models have two drawbacks: first, they do not accurately capture the physics of degradation in copper dual-damascene (CuDD) metallization, and second, they fail to model the inherent resilience in a circuit that keeps it functioning even after a wire fails. This work overcomes both limitations. For a single wire, our probabilistic analysis encapsulates known realities about CuDD wires, e.g., that some regions of these wires are more susceptible to EM than others, and that void formation/growth show statistical behavior. We apply these ideas to the analysis of on-chip power grids and demonstrate the inherent robustness of these grids that maintains supply integrity under some EM failures.

This paper presents an efficient algorithm for the placement of power supply pads in flip-chip packaging for high-performance VLSI circuits. The placement problem is formulated as a mixed-integer linear program (MILP), subject to the constraints on mean-time-to-failure (MTTF) for the pads and the voltage drop in the power grid. To improve the performance of the optimizer, the pad placement problem is solved based on the divide-and-conquer principle, and the locality properties of the power grid are exploited by modeling the distant nodes and sources coarsely, following the coarsening stage in multi-grid-like approach. An accurate electromigration (EM) model that captures current crowding and Joule heating effects is developed and integrated with our C4 placement approach. The effectiveness of the proposed approach is demonstrated on several designs adapted from publicly released benchmarks.

In the period of extreme CMOS scaling, reliability issues are becoming a critical problem. These problems include issues related to device reliability, in the form of bias temperature instability, hot carrier injection, time-dependent dielectric breakdown of gate oxides, as well as interconnect reliability concerns such as electromigration and TSV stress in 3D integrated circuits. This tutorial surveys these effects, and discusses methods for mitigating them at all levels of design.