This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient (~ 1 pJ/bit) transceivers over extremely short (≤ 100 cm) ranges. In an attempt to design such wireless interconnects, first a model for the wireless communication channel properties is developed. The use of CMOS-based energyefficient on-off keying (OOK) transceiver architectures operating in the 60-90 GHz bands is considered as a practical solution. In order to address strict performance requirements of wireless HPC interconnects, and taking advantage of the recent developments in device scaling, compact low-power and innovative circuits based on novel double-gate MOSFETs (DG-MOSFETs) are proposed in the implementation of the architecture. The performance of a compact low-noise amplifier (LNA) design using common source (CS) inductive degeneration with 32 nm DGMOSFETs is investigated by quantitative analysis and simulation. The proposed inductor-less two-stage cascode cascade LNA is optimized for 90 GHz operation and has the advantage of gain switching over its CMOS counterpart without the use of additional switching transistors, which makes it remarkably power efficient and faster. As further examples of efficient and compact DG-MOSFET circuits for OOK transceiver design, a three-stage CS 5 dB tunable power amplifier operating up to 90 GHz, and a novel 90 GHz voltage controlled oscillator are also presented. This is followed by the proposal of an array of four monopole antennas studied using full-wave EM solver.

With the rise of chip multiprocessors, an energy-efficient communication fabric is required to satisfy the data rate requirements of future multi-core systems. The Network-on-Chip (NoC) paradigm is fast becoming the standard communication infrastructure to provide scalable inter-core communication. However, research has shown that metallic interconnects cause high latency and consume excess energy in NoC architectures. Emerging technologies such as on-chip wireless interconnects can alleviate the power and bandwidth problems of traditional metallic NoCs. In this paper, we propose A-WiNoC, a scalable, adaptable wireless Network-on-Chip architecture that uses energy efficient wireless transceivers and improves network throughput by dynamically re-assigning channels in response to bandwidth demands from different cores. To implement such adaptability in our network at run-time, we propose an adaptable algorithm that works in the background along with a token sharing scheme to fully utilize the wireless bandwidth efficiently. Since no wireless NoC design has been completely realized with current technology, we describe technology trends in designing energy-efficient wireless transceivers with emerging technologies. We compare our proposed A-WiNoC to both wireless and wired topologies at 64 cores, with results showing a 1.4-2.6× speedup on real applications and a 54 percent improvement in throughput for synthetic traffic. Using Synopsys Design Compiler, our results indicate that A-WiNoC saves 25-35 percent energy over other state-of-the-art networks. We show that A-WiNoC can scale to 256 cores with an energy improvement of 21 percent and a saturation throughput increase of approximately 37 percent.

With the increasing number of cores in chip multiprocessors, the design of an efficient communication fabric is essential to satisfy the bandwidth and energy requirements of multi-core systems. Scalable Network-on-Chip (NoC) designs are quickly becoming the standard communication framework to replace bus-based networks. However, the conventional metallic interconnects for inter-core communication consume excess energy and lower throughput which are major bottlenecks in NoC architectures. On-chip wireless interconnects can alleviate the power and bandwidth problems of traditional metallic NoCs. In this paper, we propose an adaptable wireless Network-on-Chip architecture (A-WiNoC) that uses adaptable and energy efficient wireless transceivers to improve network power and throughput by adapting channels according to traffic patterns. Our adaptable algorithm uses link utilization statistics to re-allocate wireless channels and a token sharing scheme to fully utilize the wireless bandwidth efficiently. We compare our proposed A-WiNoC to both wireless/electrical topologies with results showing a throughput improvement of 65%, a speedup between 1.4-2.6X on real benchmarks, and an energy savings of 25-35%.