The automotive industry is going through a tremendous evolution of its Electrical/Electronic architectures, based on heterogeneous computing units on the same centralized fail-safe hardware. To access the different sensors/actuators dispatched all over the vehicle, these architectures use various communication protocols, each offering a certain degree of determinism and real-time guarantees. However, when multiple data streams pass through these protocols to reach the interoperable computing units, it becomes hard to maintain a consistent data set in the distributed processing environment. To ensure these end-to-end guarantees, we define a Data Sharing Management (DSM) system that acts as a multi-protocol gateway between different components of the processing environment. Evaluation results of the FPGA-based implementation show that the additional latency induced by this DSM is less than 2% (4,276us) of the end-to-end Ethernet latency and less than 6% (370ns) of the end-to-end PCIe latency.

Data flow formalisms are commonly used to model systems in order to solve problems of buffer sizing and task scheduling. A prerequisite for static analysis of a modeled system is the existence of a periodic schedule in which the sizes of communication channels can be bounded for an unbounded execution (consistency), and that communication dependencies do not introduce a deadlock in such an execution (liveness). In the context of Cyber-Physical Systems, components are often interfaced with the physical world and have frequency constraints. The existing data flow formalisms lack expressiveness to fully cover the expected behavior of these components. We propose an extension to Synchronous Data Flow (SDF) formalism, called Polygraph, that includes frequency constraints and adjustable communication rates. We show that with these extensions, the conditions for a model to be consistent and live are no longer sufficient, and we extend the corresponding theorems with necessary and sufficient conditions to preserve these properties. We also introduce a framework to check the liveness of a Polygraph model, implemented in the tool DIVERSITY, along with preliminary experiments to validate this approach.

Hypervision is being widely implemented in an effort to control costs and to simplify management through consolidation of servers. It has been recently unraveled that well over a third of virtualization vulnerabilities reside in the hyper-visor, mostly due to hypervisor escape. The exploitation of these vulnerabilities allows an attacker, among other things, to access and/or modify data of other Virtual Machines (VMs) by escaping from its VM and executing malicious code in the hypervisor. This paper introduces the general idea of blind hypervision, a hardware/software co-design to prevent such attackers to access private elements of other VMs. Blind hypervision limits the rights of the hypervisor regarding memory access, so that a malicious agent executing with hypervisor rights cannot access the data of the VMs.

When using vector clocks to synchronize processes in a computation, the problem of the vector clock dimension is well known and an acknowledged difficulty. In dataflow process networks, a compiler can rely on some process properties to create a hierarchical view of inter-process synchronization, achieving bounded vector clock dimension. In this paper, we present two approaches to reduce the vector clock dimensions, these approaches can be clearly combination between them. The first one is mainly based on run length encoding heuristic, the second one is achieved by means of 0/1 integer programming model with modeling into the graph partitioning problem.

The ever-growing number of cores in Chip Multi-Processors (CMP) brings a renewed interest in stream programming to solve the programmability issues raised by massively parallel architectures. Stream programming languages are flourishing (StreaMIT, Brook, ∑C, etc.). Nonetheless, their execution support have not yet received enough attention, in particular regarding the new generation of many-cores.