Recently, companies such as Google, Meta (Facebook), and Microsoft reported in the mainstream press about seemingly random errors which, initially undetected ("silently"), had crept into their large cloud data centers. These reports mentioned that very specific instructions were intermittently incorrectly executed, propagated through the operating system, and would potentially manifest themselves as application-level errors. Are the root causes of these so-called silent data errors test escapes and/or reliability issues? Why are they only noticed now? Is that only the case because such large server farms bring together larger numbers of CPUs than ever seen before? And what counter measures can we take against them?

In sub 10 nm nodes, the growing dominance of interconnects in chips poses challenges in designing large-size static random-access memory (SRAM) subarrays. The main issue is the write failure problem arising from the increased resistance and capacitance for bitline (BL) and wordline (WL). To tackle this issue, the SRAM subarray design incorporates conventional (Conv.) divided WL and divided BL techniques based on 14-Å-compatible (A14) nanosheet (NS) technology. This approach allows for various subarray sizes with successful write operations, resulting in improved subarray-level performance and power (PP). However, the additional logic gates come with an area penalty that may degrade the overall performance, power, and area (PPA) at the macro level due to increased inter-subarray interconnect overhead. To overcome this limitation, the active interconnect (AIC) design is proposed with the features of fabricating another or multiple active regions at the back-end of line (BEOL) layers. By moving these extra logic gates from front-end of line to BEOL in the AIC divided subarray design, the area penalty is significantly mitigated without compromising PP compared to the standard (Std.) and Conv. divided counterparts. To achieve this concept, carbon nanotube gate-all-around transistor is explored as potential BEOL-compatible device. In this research, a comprehensive design-technology co-optimization analysis is conducted to verify the value and potential benefits of up to 65% macro-level energy-delay-area product improvement by AIC divided subarray design compared to the Std. subarray design.

Due to technology scaling in modern computing platforms, the safety and reliability issues have increased tremendously, which often accelerate aging, lead to permanent faults, and cause unreliable execution of applications. Failure in some computing systems like avionics may cause catastrophic consequences. Therefore, managing reliability under all circumstances of stress and environmental changes is crucial in all abstraction layers, from application to transistor levels. Machine learning techniques are recently being employed for dynamic reliability estimation and optimization. They can adapt to varying workloads and system conditions. This paper presents reliability improvement approaches from multiple perspectives-from transistor-level to application-level-and discusses their effectiveness and limitations as well as open challenges.

This paper presents an extensive study of 6T-SRAM based on FinFET for advanced technology nodes beyond 5nm. We deduce that parasitic resistance becomes the main bottleneck for SRAM design at these nodes. SRAM's writing margin and read speed are impacted due to the increased Bit-Line (BL) and Word-Line (WL) resistance. This work primarily explores two possible solutions to improve the parasitic resistance at advanced process technology nodes: 1) strapping of BL and WL to higher metal, and 2) adopting the resistance optimized BEOL. Strapping BL and WL to higher metal layer improves the Write Trip Point (WTP) by ~100mV and the critical path delay by 24% at the cost of 50% higher energy. Resistance optimized BEOL can improve WTP by ~50mV more and delay by 25% more, at the cost of increased energy consumption (8%).

In this paper, we introduce a novel design of a 3D static random-access memory (SRAM) macro in a 3D Nanofabric process technology. The 3D Nanofabric technology is based on enabling the processing of N stack of identical layers simultaneously regardless of the number of stacked layers which consequently reduces the fabrication cost as well as the footprint of SRAM macros. To enable simultaneous patterning of stacked layers, 3D Nanofabric requires circuit topology and layout that rely on a single layer where the device channel, poly, and metal wires are all embedded without any other crossing than the gate on top of the device channel. Accordingly, we modify the layouts of the conventional SRAM bit-cell and periphery circuits which are complex and contain several metal crossings. Furthermore, we propose a new overall organization of the 3D SRAM macro that incorporates a stack of multiple identical layers each consisting of an equal size 2D array of bit-cells and the periphery circuits. We show that the proposed 3D Nanofabric SRAM macro offers 71.2% footprint gain and 36.3% read access speed improvement compared to equal size 2D SRAM macro in 3 nm FinFET.

Due to the rise in the number of cores in modern multicore architectures, 3-D integration (i.e., vertical stacking of chips) of system-on-a-chip (SOC) promises better performance due to a drastic reduction in global interconnect lengths and die footprint compared with 2-D counterparts. However, thermal issues are predominant in 3-D-SOCs due to the vertical stacking nature of chips which multiplies the transistor power density by the number of dies within the stack. Also, the reduced lateral heat spreading with aggressive die thinning degrades the ON-chip thermal performances. In this article, we investigate the thermal performance analysis of 3-D-SOC and compare the results with the 2-D-SOC designs for a MemPool multicore SOC with shared L1 scratchpad memory (SPM). Simulation results reveal that the 3-D-SOC using memory-on-logic (MOL) configuration increases the ON-chip maximum temperature by more than 20% compared with the baseline 2-D-SOC and the logic die temperature is relatively higher (3.6%) than the memory die. We also explore the impact of architectural floor-planning effects and 3-D functional partitioning on thermal performance of the MemPool instances in the 3-D-SOC with memory capacity ranging from 1 to 8 MiB and benchmarked the thermal performance with the 2-D-SOC designs. We observe that the junction-to-ambient temperature ($T_{\max }$) increases by 44% and is predominant for the SPM capacity of 8 MiB. Further investigations on various 3-D stacking configurations reveal there is an improvement in thermal performance for MOL over logic-on-memory (LOM) for L1 SPM capacity of 1, 2, and 4 MiB, and LOM over the MOL configuration for L1 SPM capacity of 8 MiB.

Energy saving is important for both high-end processors and battery-powered devices. However, for time-critical application such as car auto-driving systems and multimedia streaming, saving energy by slowing down speed poses a threat to timing guarantee of the applications. The worst-case execution time (WCET) is a widespread solution to this problem, but its static execution time model is not sufficient anymore for highly dynamic hardware and applications nowadays. In this work, a fully proactive run-time mitigation methodology is proposed for energy saving while ensuring timing guarantee. This methodology introduces heterogeneous datapath options, a fast fine-grained knob which enables processors to switch between datapaths of different speed and energy levels with a switching time of only tens of clock cycles. In addition, a run-time controller using a dynamic scenario methodology is developed. This methodology incorporates execution time prediction and timing guarantee criteria calculation, so it can dynamically switch knobs for energy saving while rigorously still ensuring all timing guarantees. Simulation shows that the proposed methodology can mitigate a dynamic workload without any deadline misses, and at the same time energy can be saved.

Novel devices that optimize their structure in a three-dimensional fashion and offer significant area gains by reducing standard cell track height are adopted to scale silicon technologies beyond the 5nm node. Such a device is the Complementary FET (CFET), which consists of an n-type channel stacked vertically over a p-type channel. In this paper we review the significant benefits of CFET devices as well as the challenges that arise with their use. More specifically, we focus on the standard cell design challenges as well as the physical implementation ones. We show that to fully exploit the area benefits of the CFET devices, one must carefully select the metal stack used for the physical implementation of a large design.

Ensuring a timing guarantee is crucial for time-critical applications. However, this task becomes more challenging with the increasing performance variability generated by complicated modern hardware and software. A widespread solution to the problem is real-time scheduling, which depends on worst-case execution time (WCET) and dynamic voltage frequency scaling (DVFS). Although these techniques provide the necessary guarantees, they also exhibit important limitations from the long switching time of DVFS and the overly pessimistic execution time model of WCET. In this work, a multitimescale mitigation methodology is proposed to improve the way of tackling performance variability in both timing guarantee and energy saving. By using both the DVFS and heterogeneous datapath (HDP) knobs, this methodology can push the timescale of mitigation down to the submillisecond level. Moreover, this methodology can calculate a tight upper bound of execution time at run-time using dynamic scenarios (DSs). Simulation shows that the proposed methodology can ensure zero deadline misses with a smaller safety time margin than the method using only DVFS and WCET. This advantage can translate into an energy reduction by half compared to the conventional WCET-based method with a single DVFS knob.

In this article, we provide a comprehensive evaluation of width modulation capabilities of both nanosheet (NS) and forksheet (FS) devices, going from device level to a block level implementation. The main innovation introduced by the FS consists of a dielectric wall added between the p- and nMOS transistors. Leveraging this feature, FS shows approximately the same current behavior as NS, considered a state-of-the-art reference, but reduced parasitic capacitance thanks to its fewer but wider stacked sheets. At block level, an area reduction up to 12% is observed with FS, alongside a 13% power reduction and 10% frequency increase. Following the device comparison, the potential of sheet width modulation as additional power, performance, and area (PPA) optimization technique during synthesis and place and route (PNR) is investigated. A description of the specific steps required to enable this knob in a conventional electronic design automation (EDA) framework is provided. As demonstrated by the obtained experimental results, the same frequency of the single-width implementation can be achieved using mixed libraries with lower power consumption (13% and 16% for NS and FS, respectively), leading to improved energy efficiency. Furthermore, it is shown how designs implemented using FS benefit more from this type of optimization than the ones using NS, with a 12%–15% energy reduction compared to the 8.5%–14% obtained with NS.

The presence of multiple cores in modern multicore architectures makes thermal management and temperature estimation a really challenging task for enhancing reliability and lifespan. Due to the presence of many cores, the core/tile spacing needs to be optimized in order to enhance the thermal coupling between interconnect routing blocks and active tiles. In addition, the tiles activity patterns under partial workload conditions significantly affect the maximum on-chip temperature which results in nonuniform temperature distribution. This is due to poor thermal coupling between neighboring tiles owing to the decrease in spacing between cores. In this article, we investigate the thermal performance analysis of a 256-core (i.e., 64 tiles) Mempool reduced instruction set computer (RISC) V-based architecture considering the impact of inter tiles spacing. Simulation results reveal that lateral heat spreading predominantly affects the thermal performance in multicore architectures under partial workload conditions. We also optimize the thermal performance with different tiles activity pattern. Simulation results reveal that both the maximum on-chip temperature and lateral heat spreading are improved for specific tiles activity patterns. Also the thermal performance analysis considering the “tile-insite effect” reveals that there is little impact on on-chip maximum temperature ($T_{\text {max}}$), but the on-chip thermal gradient ($\Delta T$) and the thermal profile pattern are predominantly affected. Finally, the effect of the secondary heat path toward printed circuit board (PCB) is studied in this work.

Designers typically add design margins to semiconductor memories to compensate for aging. However, the aging impact increases with technology downscaling, leading to the need for higher margins. This results into a negative impact on area, yield, performance, and power consumption. As an alternative, mitigation schemes can be developed to reduce such impact. This paper proposes a mitigation scheme for the memory's sense amplifier (SA); the scheme is based on creating a skew in the relative strengths of the SA's cross-coupled inverters during design. The skew is compensated by aging due to unbalanced workloads. As a result, the impact of aging on the SA is reduced. To validate the mitigation scheme, the degradation of the sense amplifier is analyzed for several workloads. The experimental results show that the proposed mitigation scheme reduces the degradation of the sense amplifier's critical figure-of-merit, the offset voltage, with up to 26%.

Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, bias temperature instability (BTI) is a degradation effect that changes the threshold voltage of transistors. Its effect is more prevalent as the scaling of transistor dimensions progresses. In this work, we present a method to enable defect-centric long-term modeling of BTI degradation that takes into account the effects of concrete workloads at the processor data path level. Based on this study, we propose a novel design flow to link the impact of BTI degradation at the transistor (△Vth), processor data path (e.g., maximum frequency) and application-functionality levels. This flow may be used to improve system correctness over the entire device lifetime, avoiding unsafe working points, or to achieve a graceful degradation of system characteristics. Our design flow is applicable to all types of digital circuits, including high-performance processors. However, in this specific work we focus on the domain of biosignal processing applications for wireless body sensor networks (WBSNs), the pseudoperiodic nature of which interacts with the partially recoverable nature of BTI. Our results in this domain show, for a 32-nm implementation, a variation of up to 54.6 mV in the threshold voltage of the circuit transistors after one year of continuous operation, with an impact of 8.4% in the maximum safe operating frequency. Such effects are expected to strongly worsen for longer lifetimes and more scaled technology nodes.

Memory designs typically contain design margins to compensate for aging. As aging impact becomes more severe with technology scaling, it is crucial to accurately predict such impact to prevent overestimation or underestimation of the margins. This paper proposes a methodology to accurately and efficiently analyze the impact of aging on the memory's digital logic (e.g., timing circuit and address decoder) while considering realistic workloads extracted from applications. To demonstrate the superiority of the methodology, we analyzed the degradation of the L1 data and instruction caches for an ARM v8-a processor using both our methodology as well as the state-of-the-art methods. The results show that the existing methods may significantly over-or underestimate the impact (e.g., the decoder margin up to 221% and the access time up to 20%) as compared with the proposed scheme. In addition, the results show that in general the instruction cache has the highest degradation. For example, its access time degrades up to 9% and its decoder margin up to 44%.

Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardware-based mitigation scheme for the memory's address decoder logic. The scheme is based on adapting the decoder's workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the address decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the decoder's degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the decoder's timing margin with up to 4.1x at negligible area and no more than 3% power overhead.

Designers typically add design margins to compensate for chip aging. However, this leads to yield loss (in case of overestimation) or low reliability (in case of underestimation). This paper analyzes the impact of aging on a complete high-performance industrial 14-nm FinFET SRAM. It investigates the impact on the memory's parametric (i.e., its delay) and functional (i.e., correct functionality) metrics. Moreover, it examines which components are the main contributors to the degradation of the memory's reliability and how it is impacted by workload and environmental conditions, i.e., temperature and voltage fluctuations. This paper not only investigates the impact of the memory's components individually, which is typically the case in prior work, but it also studies the contribution of components' interaction to the overall memory aging. The results show that the timing circuit, address decoder, and the output latches and buffers are the main contributors to the memory's parametric degradation, while the cell, sense amplifier, and address decoder are the main contributors to its functional degradation. Moreover, the results show that it is crucial to consider the impact of the interaction of components on the aging; individual analysis leads to overly pessimistic results and even wrong conclusions in certain cases.

Advanced scaling and the introduction of new materials in the metal-oxide-semiconductor field-effect transistor (MOSFET) raise concerns about its reliability. Several degradation mechanisms, depending on operating conditions and time, can cause a significant change of the transistor parameters. The transistor area plays a large role when it comes to aging. In large-area MOSFETs, aging appears deterministic, while in small-area devices it is stochastic and convoluted with random telegraph noise. This is analogous to the time-zero random variability, which also reduces as the transistor gate area increases. The scope of this paper is to extend the knowledge of the time-dependent random variability as a function of MOSFET gate area scaling. The goal is to aid the designers in transistor sizing toward a more reliable design. As an example, the impact of time-dependent random variability is illustrated for an analog-to-digital converter.

Memory designs usually add design margins to compensate for chip aging; this may lead to yield and performance loss (in case of overestimation) or reduced reliability (in case of underestimation). This paper analyzes the impact of aging on cutting edge high performance 14nm FinFET SRAM using a calibrated aging model; it does not only analyze the impact of the SRAM's components individually, as it is the case in prior work, but it also investigates the contribution of the interaction of these components while considering different workloads; both the overall metric of the memory (i.e., the access time) as well as metrics of individual components (e.g., sensing delay for the sense amplifier) are examined. The results show that it is crucial to consider not only the aging of all individual components, but also their interaction in order to provide accurate prediction of aging effects; considering only aging of single/individual components leads to either too optimistic or pessimistic results. For example, using our approach (which includes the components interaction) results approximately in 9.1% degradation of memory access time (for three years of aging), while using the traditional approach (based on adding the impact of individual components) results in 7.3% increase only; a relative difference of 25%, for which the timing and the address decoder components are the main contributors. With respect to individual components, the sense amplifier is the most fragile one (e.g., its offset voltage spec. degrades up to 58%).

Device aging is an important concern in nanoscale designs. Due to aging the electrical behavior of transistors embedded in an integrated circuit deviates from original intended one. This leads to performance degradation in the underlying device, and the ultimate device failure. This effect is exacerbated in emerging technologies. To be able to tailor effective aging mitigation schemes and improve the reliability of devices realized in cutting edge technologies, there is a need to accurately study the effect of aging in high performance industrial applications. According, this paper targets a high performance SRAM memory realized in 14nm FinFET technology and depicts how aging degrades the individual components of this memory as well as the interaction between them. Aging mitigation is critical not only from device reliability point of view but also regarding device security perspectives. It is essential to assure the security of the sensitive tasks performed by the security-sensitive circuits and to guarantee the security of information stored within these devices in the presence of aging. Accordingly in this paper, we also focus on aging-related security concerns and present the cases in which aging need to considered to preserve security.

To compensate for time-zero (due to process variation) and time-dependent (due to e.g. Bias Temperature Instability (BTI)) variability, designers usually add design margins. Due to technology scaling, these variabilities become worse, leading to the need for bigger design margins. Typically, only worst-case scenarios are considered, which will not present the actual workload of the targeted application. Alternatively, mitigation schemes can be used to counteract the variability. This paper presents a run-time design-for-reliability scheme for memory Sense Amplifiers (SAs); SAs are an integral part of any memory system and are very critical for high performance. The proposed scheme mitigates the impact of time-dependent variability due to aging by using an on-line control circuit to create a balanced workload. The simulation results show that the proposed scheme can reduce the most critical figures-of-merit, namely the offset voltage shift and the sensing delay of the SA with up to ~40% and ~10%, respectively, depending on the stress conditions (temperature, voltage, workload).

The CMOS technology scaling faced over the past recent decades severe variability and reliability challenges. One of the major reliability challenges is bias temperature instability (BTI). This paper analyzes the impact of BTI on the sensing delay of standard latch-type sense amplifier (SA), which is one of the critical components of high performance memories; the analysis is done by incorporating the impact of process, voltage, and temperature variations (in order to investigate the severity of the integral impact) and by considering different workloads and four technology nodes (i.e., 45, 32, 22, and 16 nm). The results show the importance of taking the SA degradation into consideration for robust memory design; the SA degradation depends on the application and technology node, and the sensing delay can increase with 184.58% for the worst case conditions at 16 nm. The results also show that the BTI impact for nominal conditions at 16 nm reaches a 12.10% delay increment. On top of that, when extrinsic conditions are considered, the degradation can reach up to 168.45% at 398 K for 16 nm.

Designers typically add design margins to compensate for time-zero variability (due to process variation) and time-dependent (due to, e.g., bias temperature instability) variability. These variabilities become worse with scaling, which leads to larger design margin requirements. As an alternative, mitigation schemes can be applied to counteract the variability. This paper investigates the impact of aging on the offset voltage of the memory's sense amplifier (SA). For the analysis, the degradation of the SAs in the L1 data and instruction caches of an ARM processor is quantified while using realistic workloads extracted from the SPEC CPU2006 Benchmark suite. Furthermore, the effect of our mitigation scheme, i.e., an online control circuit that balances the SA workload, is analyzed. The simulation results show that the mitigation scheme reduces the offset voltage degradation due to aging with up to 40% for the benchmarks, depending on the stress conditions (temperature, voltage, and workload).

With the continuous downscaling of CMOS technologies, ICs become more vulnerable to transistor aging mainly due to Bias Temperature Instability (BTI). This paper presents a comparative study of the BTI impact while considering varying supply voltages and temperatures for three memory sense amplifier (SA) designs: low power (LP), mid power/performance (MP), and high performance (HP). As an evaluation metric, the sensing delay (SD) of the three designs is analyzed for various workloads using 45nm technology. The results show that HP SA degrades faster than MP SA and LP SA irrespective of the workload, supply voltage, and temperature. At nominal supply voltage and temperature, HP degrades up to 1.62x faster than MP, and up to 1.94x faster than LP designs for the worst case workload. In addition, the results show that an increase of 10% in power supply has a marginal impact on the relative degradation. In contrast, the results show that a temperature increment significantly worsens the BTI impact. Finally, the results show that for 16nm technology, BTI impact becomes worse and even causes read failures. This clearly indicates that designing for reliability is not only strongly application dependent, but also technology node dependent. Hence, one has to carefully consider the targeted application, design, and technology node in order to provide appropriate solutions.

This paper investigates the impact of aging in the read path of 32nm high performance SRAM; it combines the impact on the memory cell, on the sense amplifier, and on the way they interact. The analysis is done while considering different workloads and by inspecting both the bit-line swing (which reflect the degradation of the cell) and the sensing delay (which reflects the degradation of the sense-amplifier); the voltage swing on the bit lines has a direct impact on the proper functionality of the sense amplifier. The results show that in addition to the sense amplifier degradation, the cell degradation also contributes to the sensing delay increase; the share of this contribution depends on the cell design. Moreover, this sensing delay becomes worst at stressy workloads.

Atomistic-based approaches accurately model Bias Temperature Instability phenomena, but they suffer from prolonged execution times, preventing their seamless integration in system-level analysis flows. In this paper we present a comprehensive flow that combines the accuracy of Capture Emission Time (CET) maps with the efficiency of the Compact Digital Waveform (CDW) representation. That way, we capture the true workload-dependent BTI-induced degradation of selected CPU components. First, we show that existing works that assume constant stress patterns fail to account for workload dependency leading to fundamental estimation errors. Second, we evaluate the impact of different real workloads on selected CPU sub-blocks from a commercial processor design. To the best of our knowledge, this is the first work that combines atomistic property and true workload-dependency for variability analysis.

With the continuous downscaling of CMOS technologies, ICs become more vulnerable to transistor aging mainly due to Bias Temperature Instability (BTI). A lot of work is published on the impact of BTI in SRAMs; however most of the work focused mainly on the memory cell array. An SRAM consists also of peripheral circuitries such as address decoders, sense amplifiers, etc. This paper characterizes the combined impact of BTI and voltage temperature fluctuations on the memory sense amplifier for different technology nodes (45nm up to 16nm). The evaluation metric, the sensing delay (SD), is analyzed for various workloads. In contrast to earlier work, this paper thoroughly quantifies the increased impact of BTI in such sense amplifiers for all the relevant technology scaling parameters. The results show that the BTI impact for nominal voltage and temperature is 6.7% for 45nm and 12.0% for 16nm when applying the worst case workload, while this is 1.8% for 45nm technology and 3.6% higher for 16nm when applying the best case workload. In addition, the results show that the increase in power supply significantly reduces the BTI degradation; e.g., the degradation at -10%Vddis 9.0%, while this does not exceed 5.3% at +10%Vddat room temperature. Moreover, the results that the increase in temperature can double the degradation; for instance, the degradation at room temperature and nominal Vddis 6.7% while this goes up to 18.5% at 398K.

Reliability of advanced deeply scaled CMOS technologies is being threatened by time-dependent degradation mechanisms such as Negative Bias Temperature Instability (NBTI) phenomenon that cause workload-dependent shifts on a transistor's threshold voltage (VTH), and performance during its lifetime. In this study, NBTI-induced performance degradation of 32-bit adders (one of the most fundamental block of a processor's arithmetic logic unit) is investigated from the points of architectural topology, technology scaling (i.e. commercial 28, 45, 65nm nodes) and workload dependency. The selected adder architectures vary from basic to complex parallel-prefix ones. A workload-dependent, NBTI aging-aware digital design flow was developed within the industry standard EDA tool chain. NBTI model is based on the extracted Capture and Emission Time (CET) maps from the actual wafer measurements. Static Timing Analysis (STA) is performed to evaluate the performance degradation at the +3σ corner. Results on adders under the NBTI aging after 3 years show a performance loss up to 16%. NBTI aging results in the replacement of the time-zero critical path by an initially non-critical path during a circuit's lifetime. The time-zero critical path can shift to a new one with a probability of 89%. Technology scaling and the choice of process technology can impact the degradation by 2×. Finally, the performance degradation can vary up to 8.2× under workload variations.

With deeply scaled CMOS technology, Bias Temperature Instability (BTI) has become one of the most critical degradation mechanisms impacting the device reliability. In this paper, we present the BTI evaluation of a single inverter gate covering both the PMOS and NMOS degradations in a workload dependent, atomistic trap-based, stochastic BTI model. The gate propagation delay depends on the gate intrinsic delay, the input signal characteristics, and the output load. Thus, the BTI degradation is investigated due to the impact of 1) duty factor, 2) periodic clock-based and non-periodic random input sequences, 3) gate drive strength. The inverter is chosen due to its representativity of other CMOS logic gates. The applied BTI model is stochastic, and the device parameters are orthogonally generated by distributions. Results show 3% and 27% degradation shifts on the distribution mean and worst-case. In addition, it is shown that the near-critical paths with lower drive strength cells are more susceptible to the BTI degradation than the critical paths with higher drive strength cells.