The Cell-Aware (CA) methodology has become essential to detect and diagnose manufacturing intra-cell defects in modern semiconductor technologies. It characterizes standard cells by creating a defect-detection matrix, which serves as a reference that maps stimuli to the specific defects they can detect. Its limitation is that CA approach needs a number of time-consuming analog simulations to create the matrix. In [1] a graph-based methodology able to reduce the number of simulations to perform, called Transistor Undetectable Defect eLiminator (TrUnDeL), was presented. TrUnDeL can identify undetectable stimulus/defect pairs that are then excluded from the analog simulations. However, its use is limited to combinational cells and does not offer any guidance on handling sequential cells, which are usually the most complex cells. In this paper we present a new version of TrUnDeL that supports sequential cells analysis. Experiments conducted on sequential cells from two standard cell industrial libraries demonstrate that the CA generation time is reduced by 30% without compromising accuracy.

Testing advanced memories is essential for ensuring modern System-on-Chip quality. As transistor size continues to shrink, the probability of the occurrence of manufacturing defects increases, making conventional functional testing of SRAMs inadequate for achieving required Defect Parts per Million (DPPM). To address this issue, a novel structural testing approach using the Cell-Aware (CA) test methodology has been proposed in [1]. With this methodology, structural test patterns are obtained through an Automatic Test Pattern Generator (ATPG) by exploiting analog CA models (i.e., based on exhaustive analog simulations) for SRAM primary blocks. However, the generation of CA models through analog simulations is time-consuming and technology dependent. A methodology, namely TrUnDeL proposed in [2], is used to accelerate the CA model generation, combining a switch-level graph-based solution and analog simulations. In this work, we propose an adaptation of TrUnDeL to generate the CA models, using only the switch-level graph-based simulations. TrUnDeL CA models are then used by the ATPG to generate structural test patterns. Through a validation flow, we demonstrate that the aforementioned patterns, generated without running any analog simulations, achieve nearly the same fault coverage as the test patterns generated using exhaustive analog simulations on an SRAM case study. The time required to generate CA models is drastically reduced with TrUnDeL, from 1 hour to 15 seconds for the considered case study.

Modern integrated circuits such as System-On-Chip (SOC) require a large amount of memory. The integration density of these memories is based on the extreme miniaturization of the technological nodes. However, the miniaturization process contributes to an increase in the occurrence of physical defects. In order to verify the quality of memories, new test methods, based on structural testing, have been proposed recently. However, these methods rely on a digital test environment and require an accurate modeling of the memory. This work proposes a digital SRAM modeling compatible with digital simulation and test environments. The digital SRAM modeling presented in this paper is functionally equivalent to an analog SRAM model (i.e., memorization, Write and Read operations). The memorization capability of the model enables it to consider the data-background of the memory array during testing, facilitating the evaluation of complex test sequences, such as March algorithms, in covering structural fault models (i.e., Cell-Aware fault models).

Testing memory circuits is crucial for ensuring the quality and reliability of system-on-chip (SoC) designs, especially as shrinking technology nodes increase susceptibility to nanometer-scale defects. This article introduces an enhanced methodology for memory testing, leveraging the cell-aware (CA) test concept. Building on prior work for SRAM array testing (Xhafa et al., 2023), we extend the CA methodology to include periphery testing by generating, for the first time, CA models for each memory input–output (I/O) element, covering key components, such as address decoders, write drivers, and sense amplifiers. We present results from testing these periphery components using the CA methodology. Additionally, we compare existing SRAM testing techniques with our CA methodology for the decoder and I/O circuitry. To ensure a fair comparison, we selected minimal March tests designed to detect functional faults in peripheral circuits, aligning with the fault models targeted by our approach. A quantitative analysis of fault coverage demonstrates the effectiveness of our methodology compared to March algorithms, particularly in terms of test complexity.

The reduction in transistor size in modern Integrated Circuits (ICs) has led to an increase in manufacturing defects within standard cells, also known as intra-cell defects. Detecting these defects and localizing them through diagnosis is crucial for achieving a fast yield ramp-up and ensuring a low test escape rate. Traditional fault models, such as stuckat and transition, do not effectively represent intra-cell defects. To address this issue, the Cell-Aware (CA) methodology was introduced. However, this technique involves time-consuming analog SPICE simulations to characterize standard cells. This paper presents a methodology, called Transistor Undetectable Defect eLiminator (TrUnDeL), based on graph theory to speed up the CA model generation process. Our methodology identifies undetectable defects for each stimulus applied at the inputs of the cell, which are then excluded from the analog simulations. We applied TrUnDeL to two libraries from STMicroelectronics (P28 and C28) to identify the undetectable stimulus/defect pairs, so that analog simulations are performed only on the remaining pairs. As a result, the CA model generation process time is reduced by a factor of 3. Finally, we applied TrUnDeL to a SRAM bitcell case study and demonstrated that the obtained results are consistent with its existing CA model.

As modern Integrated Circuits (ICs) feature ever-smaller transistors, the prevalence of manufacturing defects within standard cells (intra-cell defects) has increased. Detecting and localizing these defects is crucial to guarantee a fast yield ramp-up and to maintain a low-test escape rate. Unfortunately, traditional fault models such as stuck-at and transition fail to adequately represent intra-cell defects. Cell-Aware (CA) was introduced to tackle this problem, but it requires time-consuming analog SPICE simulations for standard cell characterization. To speed-up the CA model generation process, this paper presents a methodology based on graph theory called Transistor Undetectable Defect Eliminator (TrUnDeL). This methodology identifies undetectable defects for each stimulus applied to the inputs of the cell, subsequently excluding them from the analog simulations to perform. TrUnDeL uses rule-based and propagation-based techniques and was trialed on combinational and sequential cells of two 28nm libraries from STMicroelectronics (P28 and C28) to identify the undetectable stimulus/defect pairs, so that analog simulations are performed only on the remaining pairs. As a result, the CA model generation process time was reduced by a factor of 3 compared to a standard SPICE-based generation process.

The shrinking of technology nodes has led to high density memories containing large amounts of transistors which are prone to defects and reliability issues. Their test is generally based on the use of well-known March algorithms targeting Functional Fault Models (FFMs). This paper presents a novel approach for memory testing which relies on Cell-Aware (CA) methodology to further improve the yield of System on Chips (SoCs). Consequently, using CA methodology converts memory testing from functional to structural testing. In this work, the preliminary flow of the CA-based memory testing methodology is presented. The generation of the CA model for the SRAM bit cell has been demonstrated as a case study. The generated CA model and the structural representation of the memory are used by the ATPG to test the bit cell in the presence of short and open defects. The generated test patterns are able to detect both static and dynamic faults in the bit cell with a test coverage of 100%.

We demonstrate a Hardware Trojan (HT)-based circuit-to-circuit attack mechanism in the context of Systems-on-Chip (SoCs). The HT trigger is hidden inside the attacking circuit and the HT payload travels from the attacking circuit to the victim circuit via the test infrastructure. The common test infrastructure is configured accordingly by the HT so as to propagate the HT payload. We demonstrate the capability of this HT to perform a denial-of-service attack on an industrial Analog-to-Digital Converter (ADC) connected to a IEEE 1687 test infrastructure.

Hardware Trojan (HT) insertion is a major security threat for electronic components that demand a high trust level. Several HT attack mechanisms have been demonstrated to date, and several HT prevention and detection countermeasures have been proposed to thwart HT attacks. Given the multitude of HT attack mechanisms, run-time monitors for HT detection are used as a last line of defense. In this paper, we propose a run-time monitoring methodology for HT attack mechanisms affecting the analog and mixed-signal (AMS) sections of an Integrated Circuit (IC). The methodology is based on the Symmetry-based Built-In Self-Test (SymBIST) principle that relies on distributing invariances across the IC and continuously checking for their compliance. Detection of various HT attacks are demonstrated on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP at transistor-level.

Fault diagnosis methodologies for analog circuits lag far behind those for their digital counterparts. In this paper, we show how the generic Symmetry-based Built-In Self-Test (BIST) (or SymBIST), originally proposed for defect-oriented post-manufacturing test and on-line test, can be seamlessly reused for the purpose of diagnosis. BIST can offer better insights into the circuit and, thereby, can assist diagnosis towards resolving ambiguity groups. Using SymBIST we demonstrate high diagnosis resolution and fast diagnosis cycle for an industrial Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC).

We propose a Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (SymBIST). SymBIST exploits inherent symmetries in an A/M-S IC to construct signals that are invariant by default, and subsequently checks those signals against a tolerance window. Violation of invariant properties points to the occurrence of a defect or abnormal operation. SymBIST is designed to serve as a functional safety mechanism. It is reusable ranging from post-manufacturing test, where it targets defect detection, to on-line test in the field of operation, where it targets low-latency detection of transient failures and degradation due to aging. We demonstrate SymBIST on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). SymBIST features high defect coverage, short test time, low overhead, zero performance penalty, and has a fully digital interface making it compatible with modern digital test access mechanisms.

In this paper, we propose a defect-oriented Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/MS) Integrated Circuits (ICs), called symmetry-based BIST (Sym-BIST). SymBIST exploits inherent symmetries into the design to generate invariances that should hold true only in defect-free operation. Violation of any of these invariances points to defect detection. We demonstrate SymBIST on a 65nm 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP by ST Microelectronics.

In critical (e.g. automotive) applications, Systems-on-Chip (SoC) failures that occurred during mission mode (in the field) are the most critical since they may lead to catastrophic effects. In this context, diagnosis is crucial in order to establish the root cause of observed failures with the best accuracy. With the advent of very deep submicron technologies (i.e. 7 nm), achieving such level of accuracy will become more and more difficult with today's intra-cell diagnosis tools based on effect-cause or cause-effect paradigms. This will compromise the success of subsequent Physical Failure Analysis (PFA) done on defective SoCs. Machine Learning (ML) is now used in numerous classification problems where the knowledge on some data can be used to classify a new instance of such data. In particular, several ML-based solutions exist to address volume diagnosis for yield improvement. These learning-guided diagnosis approaches start from an existing set of defect candidates and try to minimize this set (eliminate bad candidates) owing to the use of ML tools and numerous data collected during production test (e.g. thousands of failed chips with candidates correctly labeled). Although efficient in volume diagnosis, these approaches cannot be used to identify the root cause of failures in customer returns, since only one failed chip is investigated in this case, with no information about the defective behavior of some other similar chips used in the same conditions (environment, workload, etc.). In this paper, we propose a new learning-guided approach for diagnosis of mission mode failures in customer returns. The proposed approach directly produces a minimum set of good candidates derived from the application of the learning-guided intra-cell diagnosis flow. Results obtained on a set of benchmark circuits, and comparison with a commercial intra-cell diagnosis tool, show the feasibility, effectiveness and accuracy of the proposed approach.

In today's electronic designs, more and more memories are embedded in a single chip. The latest technologies make them denser and thus defects due to the manufacturing process are more prone to occur not only in the array but also in the periphery of the memory. A fast and accurate localization of such defects has become much more difficult with traditional diagnosis approaches that do not allow a fast-enough yield learning and improvement. This paper describes a new and automated intra-cell diagnosis flow for SRAMs to precisely determine the root cause of observed failures during test. Based on the electrical and topological fault signatures obtained through traditional methods, each potential fault on the identified active nets is automatically simulated to retrieve the best defect candidates to precisely guide the Failure Analysis phase. The proposed intra-cell diagnosis flow has been experimented on simulated test cases as well as silicon (industrial) test cases. The results obtained demonstrate the effectiveness of the diagnosis flow in terms of low number of defect candidates. Moreover, for the silicon test cases, these diagnosis results match with the ongoing Failure Analysis reports.

Failure bitmaps of manufactured memory arrays may contain the information of some systematic defects and have hence been used to monitor the process and to improve the memory yield. It is important to have an accurate flow to classify the memory failure bitmap signatures. The memory bitmap signature classification can be either dictionary based or machine learning based. This paper introduces a hybrid flow that can combine dictionary based and machine learning based methods. The proposed method can enhance the accuracy of signature classification, and more importantly, it has the capability of learning new memory bitmap signatures unseen before.