Field-programmable gate array (FPGA) is a preferred solution for a CMOS image sensor (CIS) automatic test equipment (ATE) because it provides fast upgradability for the timely testing of CIS products using a new interface protocol. However, implementing a Mobile Industry Processor Interface (MIPI) C-PHY receiver to receive images from the CIS in an FPGA can be challenging due to the use of three wires, three distinct voltage levels, and the requirements of fast clock data recovery (CDR) lock time and wide CDR tracking bandwidth. To overcome these challenges, we have developed an FPGA-only MIPI C-PHY receiver that utilizes a blind oversampling CDR technique, which offers fast CDR lock time and wide CDR bandwidth. We used an Altera Stratix 10 GX FPGA as an oversampling device by operating its transceiver in a lock-to-reference-clock mode. We developed a parallel gate-based clock recovery algorithm and a fork and join-based data decision algorithm. As a result, we were able to test CIS wafers at symbol rates of up to 3.5 Giga-symbols per second, achieving performance comparable to that of sophisticated ASIC-based CIS ATEs.

Evaluating the clock quality of a device's phase-locked loop (PLL) using automatic test equipment (ATE) at an affordable cost is challenging due to the large number of channels and long test times required. This study proposes a new low-cost method for testing the clock jitter of the device using PLL, delay, gate, etc. in the FPGA. Using this circuit, the total jitter analysis function of an expensive, heavy, and slow oscilloscope can be performed simultaneously with tens of CH of clocks within 1us time on a smart phone size board with only tens of dollars of FPGA.

During wafer testing with probe cards in Automatic Test Equipment (ATE), it is challenging to maintain a stable VDD-GND voltage supplied to the Device Under Test (DUT) due to fluctuations in GND voltage caused by the return current from the DUT. Typically, due to a lack of channels, the test equipment reads and corrects the VDD voltage based on the representative GND voltage at an intermediate point where power is supplied, rather than the ground of each DUT. As a result, if there is a change in the GND voltage of each DUT, the test equipment is unable to detect and adjust for it. To overcome these limitations, this study proposes a method of configuring a circuit within the probe card that allows for the use of existing equipment functions such as current measurement and open-short testing while correcting changes in the individual DUT GND voltage of sensitive power sources. This approach aims to minimize wrong defect determination caused by changes in GND voltage during wafer testing.

When measuring the DC drive capability of the DUT's output pin in ATE, the DUT's output voltage is often measured with a termination resistor such as 100 ohms for a differential signal or 50 ohms for a single-ended signal. In this case, as the tester must always be accurate, it is important to create an accurate termination resistance condition. In addition, in some cases, it is desirable to measure the output voltage of the signal pin under different termination conditions. This paper presents a method of correcting an inaccurate termination resistance value or changing a termination resistance value to another value by using the current output function of a parametric measurement unit (PMU) in a tester with only one representative load resistor. In this way, the termination resistance deviation between equipment and CH can be evenly calibrated, and if a test is required under new termination resistance conditions that are not mounted on the tester, the test can be performed only by modifying the software without modifying H/W.

If a transmission line carrying a high-speed signal is damaged, for example by poor contact, the transmitted signal will have a slight increase in jitter. Normally, an oscilloscope or a Vector network analyzer (VNA) is required to measure this jitter increase. In this study, we will show that it is possible to diagnose small losses in transmission lines using only an FPGA without instruments by transmitting a pulse signal through the CH to be diagnosed and then oversampling it in an FPGA to statistically accurately measure the width of the transmitted pulse and detect the small pulse width reduction that occurs when a loss occurs.

As signal transmission loss in automatic test equipment (ATE) is large, receiving a signal without an equalizer is difficult. This study designs a 4.5 Gsps mobile industry processor interface (MIPI) D-PHY analog front-end receiver circuit for ATE. The D-PHY signal uses a DC-coupled low-voltage signal, making the use of commercially available continuous time linear equalizer (CTLE)-included redrivers difficult. We propose a receiving circuit with an equalizer as an off-the-shelf device that can receive D-PHY signals from long distances. The developed receiving circuit achieved optimal signal restoration performance by tuning for the fixed loss characteristics. Additionally, using this receiving circuit, we verified the complete output-signal conversion into an image in a wafer mass production environment.

This paper presents a 3.5Gsps MIPI C-PHY analog front-end receiver circuit for Automatic Test Equipment. This circuit has two features. First, it is made entirely of off-the-shelf components. Second, it has powerful CTLE to compensate for transmission line loss. Since it does not use ASIC, it is possible to add functions at a low cost and in a short time. In the wafer test environment, the loss between the wafer and the receiving circuit is large. This CTLE can be fine-tuned and effectively compensate for the transmission line loss of the developed equipment.

A circuit for on-chip measurement of duty cycle for unknown clock is demonstrated. The circuit consists of variable delay, counter and AND gate, and can be implemented on FPGA that has variable delay element without any external supporting circuit and occupies a very small portion of the FPGA. The major benefit over the previous measurement technology is that statistical analysis of the duty cycle of a large number of continuous clock cycles is possible through a single measurement.

A multi-GHz arbitrary timing generator (ATG) design is described and demonstrated in a hardware prototype. The objective of the ATG is to realize ATE hardware that nearly matches the unlimited timing flexibility of software simulation tools. The ATG allows timing edges to be programmed at almost any desired point within the test, with minimal constraints. The delay of every edge can be changed on a cycle-to-cycle basis. The period (frequency) can be changed on a bit-by-bit basis. Real-time algorithmic calculation of timing values is accomplished using a pipelined FPGA controller so that highly complex timing sequences can be synthesized. The ATG generates timing edges according to the FPGA calculations, and combines these with serialized digital “pattern” data to create the desired signal waveforms. A prototype supports ∼10ps resolution and achieves approximately +/−20ps accuracy (including 6σ random jitter). Its maximum sustainable data rate is 3.2Gbps (non-multiplexed) and 6.4Gbps (multiplexed). Bursts patterns up to 10.0Gbps are also demonstrated. Minimum pulse-width is ∼70ps.