With the accelerated global energy transition, there is an increasing demand for photovoltaic (PV) inverters with higher efficiency and power density. However, traditional silicon-based devices are approaching their physical limits, constraining opportunities to further enhance the performance of PV inverter systems. GaN HEMT offers a promising alternative to silicon-based devices, due to its superior characteristics such as low switching loss and compact device size. This paper presents the design of a 5kW single-phase two-stage PV inverter using GaN HEMTs, highlighting their power density and efficiency advantages for residential PV applications. The study focuses on the operating principle of the system, control strategy, passive device design, and a detailed loss evaluation of the inverter. A prototype is developed, featuring a peak efficiency of 98.57% and a power density of 1.254 kW/L.

In three-level neutral-point clamped (NPC) converters, carrier-based techniques are widely applied to solve the inherent capacitor voltage balancing problem as well as the common-mode voltage (CMV) mitigation. This article proposes a novel approach to simultaneously address the voltage balancing and CMV issues in a three-phase three-level single-end inverter. It can reduce the dv/dt actions (33%-66%) as well as restricting the CMV magnitude to one-sixth of DC voltage while eliminating the low-frequency voltage oscillation at the dc-ink neutral point. The proposed control method cohesively combines two methods (Method I and Method II) and selects them according to the neutral point (NP) voltage balancing condition. Method I generates four dv/dt actions in a switching cycle with higher voltage balancing ability while Method II only generates two dv/dt actions in a switching cycle with lower voltage balancing ability. Experiments are performed to validate the proposed control method. Additionally, this work observes and investigates the non-ideal phenomenon in practical circuits that causes spikes in the CMV that should have been eliminated from the modulation point of view, which have not been well studied in the literature where explanations and solutions are provided.

In SiC inverter-fed motor drives, fast-switched power devices escalate the reflected wave phenomenon, causing overvoltage oscillations at the motor terminals with shorter cable lengths between the inverter and motor. Likewise, overvoltage oscillations manifest at motor neutral point due to the reflection of inverter common-mode voltage through the machine windings. Despite extensive research on motor terminal overvoltage mitigation, the motor neutral point overvoltage remains insufficiently addressed in the literature, although it can have a more detrimental impact on the machine winding insulation especially if the high switching frequency of SiC inverters aligns with the machine antiresonance frequency. This paper evaluates the effectiveness of three passive filter designs (R, RC, and C filter) connected between the motor neutral point and grounded frame for neutral point overvoltage mitigation. The paper provides mathematical design guidelines for the parameter selection of the three filters while assesses their performance in mitigating the motor neutral point overvoltage. An experimental evaluation using a 2.2kW SiC-based motor drive setup is presented, demonstrating the effectiveness of the three filter designs to eliminate the motor neutral point overvoltage while highlighting the pros and cons of each filter design.

While the conventional methods are based on sinusoidal excitations to parameterize the loss of magnetic components, recent studies have justified the characterization directly through large-signal, rectangular excitations, as are experienced in typical power electronics converters. The Triple Pulse Test (TPT) has been proposed previously for this purpose as a discontinuous procedure to characterize the high-frequency loss of magnetics. The excitation circuit used to deliver the TPT is advanced in this paper by removing the need for two external power supplies. Instead, a single power supply is connected to a voltage-offsetting input stage which uses a novel implementation of a half-bridge circuit to deliver a controllable offset between two capacitor banks. This dc-link offsetting circuit can compensate the asymmetric voltage drops on the power devices and delivers rectangular voltages with symmetric amplitude to form closed BH loops on the device under test. The aim is for the integrated testbed is to deliver the TPT autonomously, iterating over several operating points, to generate a loss map of one magnetic component. This testbed could subsequently aid the manufacturer of magnetics to shift from material-based datasheet to component-based, which will enable the end users to model high-frequency magnetics more easily and accurately.

This paper comprehensively utilizes three control freedoms, i.e., switching state selection, zero sequence injection(ZSI) and redundant level modulation(RLM), to maintain capacitor voltage balance in two five-level three-phase converters over the full range of modulation index and power factor. The calculation process of the proposed control method is explained in detail. This method is easy to implement and can be used in other multilevel converters. The first topology is proposed for the first time in this paper. The capacitor voltage controllable region of the second topology has been extended to full operation range without extra circuits. Voltage jumps are found during the deadtime. The performance of the proposed topology and control method is verified by simulation and experiment.

Partial discharge (PD) is a prime cause of premature failure of inverter-fed motor winding insulation. With the emergence of fast-switching wide-bandgap silicon-carbide (SiC) power devices, random-wound motors are more vulnerable to highly repetitive PDs due to the high-frequency steep-fronted switching transitions that result in overvoltage oscillations at the motor terminals and non-uniform voltage distribution within the motor winding turns. This paper investigates the impact of the applied PWM voltage waveforms on the PD behavior in SiC-based inverter-fed motor drives, including two-level and three-level PWM waveforms. The electric field distribution inside insulation defects (air cavities) is analysed for the PWM voltage waveforms to theoretically predict the number and phase of probable PD events within the fundamental cycle. An experimental PD measurement setup is used to validate the theoretical analysis by applying the PWM voltage waveforms, that are generated by SiC-based power converters, on a typical turn-to-turn motor winding insulation system created by a twisted pair of enamelled magnet wire. Phase-resolved PD patterns are generated to assess the PD behavior against the PWM characteristics of each voltage waveform and the associated overvoltage pattern when power cables are used to emulate the voltage reflections in cable-fed motor drives.

To assist the engine start with the conventional three-stage aircraft starter/generator (S/G), AC excitation is usually applied to the main exciter (ME) stator winding for generating the field current through the main generator (MG) rotor winding. In this paper, a magnetic equivalent circuit (MEC) modeling approach is adopted to study the behavior of the ME, where the critical reluctances and the magneto-motive forces (MMF) are extracted for building the MEC. With the MEC model, a coupled inductor model for the ME under linear operation is derived, and the stationary ME with saturated iron is also investigated. Moreover, the decoupling of the ME rotor winding mutual inductance is discussed for simplifying the model. A simulation model for a single-phase ME with rotating diode rectifier and the MG rotor winding is built in MATLAB, and the model predicted results are presented.

The emergence of silicon carbide (SiC) power devices is considered an enabling technology toward more efficient and compact motor drives. This returns to the primary advantages of the SiC power devices, that result from their fast switching speed and elevated temperature capabilities. However, the high voltage slew rate (dv/dt) associated with the fast switching transitions has been a concern for SiC-based motor drives with interconnection power cables due to potential motor overvoltage that can degrade the winding insulation and cause premature failure. This paper proposes a quasi-three-level PWM scheme to combat the motor overvoltage oscillations in cable-fed drives with open-winding configurations. The proposed scheme reshapes the PWM voltage pulses at the inverter side to counterbalance the voltage reflections across the cable, resulting in alleviated motor overvoltage within tolerable insulation design level. The proposed scheme is conceptually illustrated in this paper and applied to dual three-phase SiC inverter for open-winding motor drives. The performance of the motor drive system under the proposed modulation scheme is verified through simulation and experimentation.

Power loss modelling of magnetic components becomes increasingly important in the design of modern power electronic converters, especially in the case of higher switching frequencies enabled by emerging wide-bandgap devices. While the modelling of the active power electronic devices is relatively mature and straightforward, the estimation of the passive magnetic component loss remains challenging, including both the core loss and winding (copper) loss. As indicated by recent studies, the accurate prediction of the core loss in power converters relies on rectangular-voltage-excited measurements. To characterize the core loss with high-frequency rectangular excitations and dc-biases, a Triple Pulse Test (TPT) has been proposed and is further extended in this paper. The TPT involves a discontinuous procedure and a bidirectional, half-bridge excitation circuit that supplies transitional high rectangular voltage and high current. The importance and practical considerations of achieving closed dynamic BH loops are discussed. The proposed TPT is analogous to the common Double Pulse Test (DPT) for power electronics devices in terms of the testing circuit, the measurement instruments, and the discontinuous procedure. Moreover, the winding loss characterization can also be achieved by the TPT, given the winding loss can be very difficult to predict especially for randomly wound components where analytical equations cannot be applied accurately. Eventually, a complete loss dataset for one magnetic component design (i.e. same core material, shape and winding arrangement) can be built from TPT, which can be utilized to accurately model the inductor loss in power converter applications.

A four-level π-type converter is a Neutral Point Clamped (NPC) multilevel converter topology for low/medium voltage applications. As the inherent issue with this topology, the DC-link capacitor voltage balancing is challenging, especially when it operates as a single-end inverter/rectifier with unity power factor. This paper proposes a closed-loop DC-link voltage balancing algorithm of a π-type converter that is effective and simple to implement. In principle, this approach is based on Redundant Level Modulation (RLM). The RLM utilizes additional voltage levels in each switching window to gain extra controllability of the DC-link capacitor voltages without affecting the average output voltage. An algorithm based on mathematical and logical operations is developed to utilize RLM to achieve the closed-loop voltage balancing. The proposed control method is effective over the full modulation index ( M=0 ~ 1.15) and full power factor range (cosφ = 0 ~ 1). The algorithm is implemented in a test rig, and the experiment confirms its effectiveness.

Multilevel converters are widely used in medium-voltage power conversion systems. In this paper, a novel five-level converter is proposed. For a three-phase system, the converter requires 30 power semiconductor devices and 12 flying capacitors in total. The required blocking voltages of all the switches are the same and the converter is suitable for medium-voltage high-power applications. A method has been proposed to control the flying capacitors' voltages. The feasibility of the proposed topology and the control method have been validated through simulation in MATLAB/Simulink.

The use of Wide Band Gap (WBG) devices in high performance power converters is becoming more common, and the range of techniques for managing the high speed switching transitions is broadening. In particular, there is now a greater interest in applying techniques for shaping the switching transients to improve the converter performance. This paper explores the current state of the art in waveform profiling gate drivers and their application to WBG devices to determine the optimum gate waveform profile. This profile is then analysed with the goal of creating a passive gate drive network capable of replicating the performance. A hardware prototype of this gate driver is demonstrated and experimental results from it are compared with those from a standard drive and a fully active driver. The active gate driver shows a 31% decrease in current overshoot or a 35.4% reduction in turn-on switching losses.

The superior electrical and thermal properties of silicon carbide (SiC), when compared to silicon (Si), has lead to it being used in power converter designs that require high efficiency and low volume. However while choosing the semi-conductor material for these high performance designs is relatively simple, the specific type of SiC device (e.g. JFET, MOSFET or BJT) is not so straight-forward. This paper compares the performance of 2-level, 3-phase DC/AC converters that were constructed with SiC MOSFETs and then SiC BJTs. From this comparison it was shown that the SiC BJT converter, using proportional regenerative gate drivers, produced results similar to the MOSFET converter whose gate drivers had an RG= 12.5Ω. The results also showed that the SiC MOSFETs could be successfully driven with zero gate resistance and the reverse recovery energy losses of the MOSFET's body diode were minimal indicating that there is no need for an additional external Schottky diode unlike the SiC BJT.

The paper presents a new four-level voltage source converter (VSC). Compared to conventional four-level converters, this proposed converter has fewer components and can be used for a higher power density system in low and medium voltage applications. Its principles and advantages are studied in this paper. The effect of various redundant switching states on the voltages of flying capacitors is analyzed. The voltages of flying capacitors can be balanced by selecting proper redundant switching states. A carrier-based pulse width modulation (CBPWM) is used to control the proposed converter. The performance of the converter is investigated and simulated in MATLAB/Simulink as well as on a 5 kVA experimental prototype.

Wide-bandgap (WBG) power devices such as SiC devices can operate at higher switching speed, higher voltage and higher temperature. While the opportunities in performance improvement with WBG devices are clear, there are significant design challenges. For example, the fast switching speed and high dv/dt can cause increased level of electro-magnetic interference (EMI), current overshoot and cross-talk effect through parasitic elements of the circuit. This paper will review the opportunities and challenges in the application of SiC devices and present several potential solutions aiming to fully exploit the supervisor characteristics of these devices while attenuating their side-effects.

With the increase of operating frequencies of switching devices, the size and weight of power converters are reduced. However, the impact of parasitic parameters becomes significant, which affects the performance of power converters. Compared with a simple equivalent circuit of filtering inductors, a detailed lumped circuit model is more suitable for the study of the behaviour of the inductor at high frequencies. The ac inductance, ac resistance and parasitic capacitance are studied respectively in this paper. The self-inductance and mutual inductance are measured to study the lumped circuit model of inductance. Because the iron core is laminated, the inductance is clearly decreased with the increase of the frequency. Meanwhile, the ac resistance is increased with the frequency because of the proximity effect and skin effect. The impact of the ac resistance and parasitic capacitance on the measured inductance are studied. The overall ac inductance is calculated and compared with the measured results to demonstrate the correctness of the analytical inductance. The ac resistance is obtained by theoretical calculation. The formulas of the turn-to-turn capacitance and turn-to-core capacitance are also derived. The overall parasitic capacitance is obtained by the theory of the electric network. Several inductors with the same inductance value but different configurations are built to investigate the overall parasitic capacitance. It has been found that the theoretical predictions agree well with the Finite Element predicted values and measured values regarding parasitic capacitance. The parasitic capacitance has negative effect on the performance of power converters. Therefore, the design parameters which can reduce the parasitic capacitance are also analysed by the theoretical predictions. The values of the influence factors and corresponding minimum parasitic capacitance are obtained by the parasitic capacitance formulas and verified by the experiment.

The auxiliary commutated pole inverter (ACPI) is a PWM soft-switching topology usually employed for switching loss reduction. This work however investigates how the two traditional ACPI control schemes, fixed- and variable-timing, can shape the transitioning edges of the inverter's output voltage. Its frequency response can then be predicted and its high-frequency content mitigated, with potential enhancements to the inverter's Common Mode Electromagnetic Interference (CM EMI) performance. By addressing the EMI problem at source, lighter passive filters might be used, beneficial to applications where high power densities are desirable. A 5-kW, 3-phase ACPI prototype is utilized for proof of concept.

Multilevel converters have gained popularity in both medium voltage and low voltage applications. To find out the connections between various multilevel voltage source converter topologies and reveal how to obtain new topologies, this paper has presented four methods to derive multilevel converter topologies. Many existing topologies as well as new topologies can be derived with the methods presented in this paper. The fundamental characteristics of the multilevel converters which determine their usability such as dc-link neutral point voltage balancing and flying capacitor voltage control are also investigated in the paper. It is expected that further topologies will be invented based on the work in the paper for emerging applications.

Today's wind turbine power is approaching 5MW and above, where medium voltage power transfer is preferred for applications in such power range. This paper has identified three generator and converter topologies suitable for medium-voltage large wind turbines. In particular, the cascaded modular converter is investigated regarding the converter topology and control strategy with a focus on low voltage ride through (LVRT) capability. The generator-side rectifier can automatically reduce the generator output power during grid voltage drop through the dc-link voltage control loop. Hence, the converter cell dc-link voltage is maintained and the active power balance is achieved. The guideline to determine the rectifier control bandwidth and to predict the generator speed increase during grid fault is given in the paper. The grid-side cascaded H-bridge converter can generate reactive power as required to support the grid voltage during grid voltage drop and the active power output is limited by the current rating of power devices. A voltage-oriented vector control scheme allows independent regulation of the active and reactive power transferred to the grid. The phase-shifted PWM used for modulating the cascaded H-bridge converter may cause unintended active power flow into and out of individual power module, which could result in the dc-link over-voltage, especially when the converter only delivers reactive power to the grid as during the grid faults. The analytical expression of the active power flow due to the modulation is derived and a solution to avoid dc-link over-voltage is given. The simulation results of a 3.3kV, 3MW system has validated the proposed converter topology and control scheme for LVRT.