ChatHPC democratizes large language models for the high-performance computing (HPC) community by providing the infrastructure, ecosystem, and knowledge needed to apply modern generative AI technologies to rapidly create specific capabilities for critical HPC components while using relatively modest computational resources. Our divide-and-conquer approach focuses on creating a collection of reliable, highly specialized, and optimized AI assistants for HPC based on the cost-effective and fast Code Llama fine-tuning processes and expert supervision. We target major components of the HPC software stack, including programming models, runtimes, I/O, tooling, and math libraries. Thanks to AI, ChatHPC provides a more productive HPC ecosystem by boosting important tasks related to portability, parallelization, optimization, scalability, and instrumentation, among others. With relatively small datasets (on the order of KB), the AI assistants, which are created in a few minutes by using one node with two NVIDIA H100 GPUs and the ChatHPC library, can create new capabilities with Meta’s 7-billion parameter Code Llama base model to produce high-quality software with a level of trustworthiness of up to 90% higher than the 1.8-trillion parameter OpenAI ChatGPT-4o model for critical programming tasks in the HPC software stack.

SYCL is a portable programming model for multivendor computing devices. Portability is critical for its success. The heterogeneous computing benchmark suite (HeCBench) is a collection of samples, benchmarks, and mini-applications from many open-source projects for heterogeneous computing. We hope that HeCBench is useful for understanding and improving performance portability in the development of the SYCL ecosystem. This abstract is a summary of the background, use cases, improvement, and future work of the benchmark suite.

Our goal is to have a better understanding of performance portability of SYCL kernels on a GPU. Toward this goal, we migrate representative kernels in bioinformatics applications from CUDA to SYCL, evaluate their performance on an NVIDIA GPU, and explain the performance gaps through performance profiling and analyses. We hope that the findings provide valuable feedback to the development of the SYCL ecosystem.

Base64 encoding has many applications on the Web. Previous studies investigated the optimizations of Base64 encoding algorithm on central processing units (CPUs). In this paper, we describe the optimizations of the algorithm on heterogeneous computing platforms. More specifically, we explain the algorithm, convert the algorithm to kernels written in CUDA C/C++ and Open Computing Language (OpenCL), optimize the CUDA and OpenCL applications with CUDA and OpenCL streams which can overlap data transfers with kernel computations, and vectorize the CUDA and OpenCL kernels to improve kernel throughput. We evaluate the impact of the number of streams upon the kernel performance on an NVIDIA Pascal P100 graphics processing unit (GPU) and a Nallatech 385A card that features an Intel Arria 10 GX1150 field-programmable gate array (FPGA). We also measure the performance and power of the applications on the CPU, GPU, and FPGA to know the advantage of each platform and the benefit of kernel offloading. The experiments show that using vector data types in the kernels is not for performance, and more work-items is better than large vectors per work-item on the GPU. OpenCL and CUDA streams can achieve almost the same performance on the GPU, but streams should be used with caution when GPU resources are underutilized. On the FPGA, kernel vectorization using 16 vector lanes can achieve the highest performance when the number of streams is one. However, increasing the vector width per work-item and the number of streams can decrease the kernel computation time for each stream, and thereby reduce the number of concurrent operations across the streams. While the raw performance on the GPU is 3.1X higher than that on the FPGA, the FPGA consumes 3.4X less power. A comparison with a state-of-the-art implementation on an Intel CPU server shows an increasing benefit of kernel offloading.

As opposed to the Open Computing Language (OpenCL) programming model in which host and device codes are written in different languages, the SYCL programming model can combine host and device codes for an application in a type-safe way to improve development productivity. In this paper, we chose two medical imaging applications (Heart Wall and Particle Filter) in the Rodinia benchmark suite to study the performance and programming productivity of the SYCL programming model. More specifically, we introduced the SYCL programming model, shared our experience of implementing the applications using SYCL, and compared the performance and programming portability of the SYCL implementations with the OpenCL implementations on an Intel® Xeon® CPU and an Iris® Pro integrated GPU. The results are promising. For the Heart Wall application, the SYCL implementation is on average 15% faster than the OpenCL implementation on the GPU. For the Particle Filter application, the SYCL implementation is 3% slower than the OpenCL implementation on the GPU, but it is 75% faster on the CPU. Using lines of code as an indicator of programming productivity, the SYCL host program reduces the lines of code of the OpenCL host program by 52% and 38% for the Heart Wall and Particle Filter applications, respectively.

There is a need to evaluate the resource usage and optimize the performance of the floating-point 2D convolution kernels on a recent FPGA which features large numbers of hardened floating-point digital signal processing blocks and an increasingly large on-chip memory. In this paper, we presented an OpenCL 2D convolution kernel with configurable parameters for specifying the precision, sizes of filter and block, vectorization width, and compute-unit duplication factor. Then, we instantiated a set of specific instances of the kernel with a fixed filter size to evaluate their resource usage and performance to narrow down the exploration space. Based on the evaluation results on an Intelo Arria 10 FPGA using high-level synthesis, we evaluated the kernels with different filter sizes within the pruned exploration space. Compared to the baseline implementation in which the vectorization width is two and the block size is 32$\times$ 32, our optimizations improve the performance by a factor ranging from 1. 9X to 3X for the single-precision kernels, and from 2. 2X to 3. 37X for the half-precision kernels. Furthermore, we evaluated the performance and power of the kernels on an Intel®Xeon®CPU and an IrisTMPro integrated GPU. We found that the FPGA could achieve the highest performance for a 9$\times$ 9 filter among the CPU, GPU, and FPGA, but the GPU can achieve the highest performance for other filter sizes.

As opposed to the OpenCL programming model in which host and device codes are written in two programming languages, the SYCL programming model combines them for an application in a type-safe way to improve development productivity. As a popular cluster analysis algorithm, k-means has been implemented using programming models such as OpenMP, OpenCL, and CUDA. Developing a SYCL implementation of k-means as a case study allows us to have a better understanding of performance portability and programming productivity of the SYCL programming model. Specifically, we explained the k-means benchmark in Rodinia, described our efforts of porting the OpenCL k-means benchmark, and evaluated the performance of the OpenCL and SYCL implementations on the Intel®Haswell, Broadwell, and Skylake processors. We summarized the migration steps from OpenCL to SYCL, compiled the SYCL program using Codeplay and Intel®SYCL compilers, analyzed the SYCL and OpenCL programs using an open-source profiling tool which can intercept OpenCL runtime calls, and compared the performance of the implementations on Intel®CPUs and integrated GPU. The experimental results show that the SYCL version in which the kernels run on the GPU is 2% and 8% faster than the OpenCL version for the two large datasets. However, the OpenCL version is still much faster than the SYCL version on the CPUs. Compared to the Intel®Haswell and Skylake CPUs, running the k-means benchmark on the Intel®Broadwell low-power processor with a CPU and an integrated GPU can achieve the lowest energy consumption. In terms of programming productivity, the lines of code of the SYCL program are 51% fewer than those of the OpenCL program.

Among brain-inspired computing paradigms, hyperdimensional (HD) computing is based on mathematical properties of high-dimensional spaces which show remarkable agreement with brain-controlled behaviors [1] . In [2] , the authors present an HD classifier for the task of identifying the language of text samples based on letter N -grams. They describe a computing architecture in which an encoding module generates a hypervector for each text sample and a search module compares the generated vector with a set of trained hypervectors. They provide an open-source implementation of their HD classifier written in hardware description language (HDL). In addition, they implemented the classifier with the 65-nm technology library, and evaluated the efficiency and accuracy of the classifier.

We choose a random network of Hodgkin-Huxley (HH) neurons with exponential synaptic conductance as a study of accelerating the simulation of networks of spiking neurons on an FPGA. Focused on the conductance-based HH (COBAHH) benchmark, we execute the benchmark on a general-purpose simulator for spiking neural networks, identify a computationally intensive kernel in the generated C++ code, convert the kernel to a portable OpenCL kernel, and describe the kernel optimizations which can reduce the resource utilizations and improve the kernel performance. We evaluate the kernel on an Intel Arria 10 based FPGA platform, an Intel Xeon 16-core CPU, and an NVIDIA Tesla P100 GPU. FPGAs are promising for the simulation of spiking neuron network.

OpenCL promotes code portability, and natively supports vectorized data types, which allows developers to potentially take advantage of the single-instruction-multiple-data instructions on CPUs, GPUs, and FPGAs. FPGAs are becoming a promising heterogeneous computing component. In our study, we choose a kernel used in frequent pattern compression as a case study of OpenCL kernel vectorizations on the three computing platforms. We describe different pattern matching approaches for the kernel, and manually vectorize the OpenCL kernel by a factor ranging from 2 to 16. We evaluate the kernel on an Intel Xeon 16-core CPU, an NVIDIA P100 GPU, and a Nallatech 385A FPGA card featuring an Intel Arria 10 GX1150 FPGA. Compared to the optimized kernel that is not vectorized, our vectorization can improve the kernel performance by a factor of 16 on the FPGA. The performance improvement ranges from 1 to 11.4 on the CPU, and from 1.02 to 9.3 on the GPU. The effectiveness of kernel vectorization depends on the work-group size.

Base64 encoding has many applications on the Web. Previous studies are focused on improving the efficiency of Base64 encoding on central processing units (CPUs). As field-programmable gate arrays (FPGAs) are becoming promising heterogeneous computing components in high-performance computing (HPC), and high-level synthesis (HLS) is more mature, we are motivated to optimize Base64 encoding on an FPGA using HLS. In this paper, we explain the algorithm, converts the algorithm to a kernel written in Open Computing Language (OpenCL), and optimize the kernel targeting an Intel Arria 10 FPGA. We evaluate the performance and power of the kernel implementations on the CPU, graphics processing units (GPUs), and FPGA computing platforms. The experimental results show that we can significantly improve the performance of Base64 encoding with the FPGA-specific optimizations. Compared to an Intel Xeon Platinum 8167 CPU, an Nvidia Tesla K80 GPU, and an Nvidia Tesla P100 GPU, the performance (the number of cycles per byte) of Base64 encoding on an Arria10-based FPGA platform is 3.98X higher than that on the K80 GPU, 17X higher than that on the CPU, and 1.83X lower than that on the P100 GPU for large input data sizes. The performance per watt on the FPGA is 1.1X lower than that on the P100 GPU, and 8.25X and 13.2X higher than that on the CPU and the K80 GPU, respectively.

Field-programmable gate arrays (FPGAs) are becoming a promising choice as a heterogeneous computing component for scientific computing when floating-point optimized architectures are added to the current FPGAs. The maturing high-level synthesis (HLS) tools, such as Intel FPGA SDK for OpenCL, provide a streamlined design flow to facilitate parallel application on FPGAs. In this paper, we evaluate and optimize the OpenCL implementations of three nuclear reactor simulation applications (XSBench, RSBench, and SimpleMOC kernel) on a heterogeneous computing platform that consists of a general-purpose CPU and an FPGA. We introduce the applications, and describe their OpenCL implementations and optimization methods on an Arria10-based FPGA platform. Compared with the baseline kernel implementations, our optimizations increase the performance of the three kernels by a factor of 35, 295, and 102, respectively. We compare the performance, power, and performance per watt of the three applications on an Intel Xeon 16-core CPU, an Nvidia Tesla K80 GPU, and an Intel Arria10 GX1150 FPGA. The performance per watt on the FPGA is competitive. For XSBench, the performance per watt on the FPGA is 1.43X higher than that on the CPU, and 2.58X lower than that on the GPU. For RSBench, the performance per watt on the FPGA is 3.6X higher than that on the CPU, and 5.8X lower than that on the GPU. For SimpleMOC kernel, the performance per watt on the FPGA is 1.74X higher than that on the CPU, and 1.65X lower than that on the GPU.

In this paper, we optimize a widely used kernel, radial basis function, in a support vector machine as a case study to evaluate the potential of using FPGAs and the capabilities of high-level synthesis (HLS) for data intensive applications. We explain the HLS flow, and use it to develop and evaluate the kernels optimized with vectorization, loop unrolling, and half-precision storage format. Our optimizations improve the kernel performance by a factor of 15.8 compared to a baseline kernel on the Nallatech 385A FPGA card that features an Intel Arria 10 GX 1150 FPGA. The half storage format can reduce the DSP and memory utilizations at the cost of increasing the logic utilization. Compared to the single-precision floating-point kernels, the half-precision kernels can reduce the dynamic power consumption on the FPGA by approximately 30%. In terms of energy efficiency, the performance per watt on the FPGA platform is approximately 3X higher than that on an Intel Xeon 16-core CPU, and 1.8X higher than that on an Nvidia Tesla K80 GPU. On the other hand, the raw performance on the FPGA is approximately 2X and 2.7X lower than that on the CPU and GPU, respectively.

Field-programmable gate array (FPGA) is a promising choice as a heterogeneous computing component for energy-aware and high-performance applications. Emerging high-level synthesis (HLS) tools such as Intel FPGA Software Development Kit for Open Computing Language (OpenCL) offer a streamlined design flow to facilitate the use of FPGAs for scientists and researchers. In this paper, we focus on the optimizations of the OpenCL design of the Bob Jenkins lookup3 hash function which is used in the open source software version of Memcached. We describe in details the optimizations of the kernel on the FPGA, and evaluate the resource utilizations, performance, and performance per watt of the kernel implementations on an Arria10-based FPGA platform. The experimental results show that the optimized design can achieve 3.46X speedup in kernel execution time compared to the baseline implementation on the Nallatech 385A FPGA card that features an Arria 10 GX 1150 FPGA chip. For the performance per watt, we achieve 8 MHash/watt on the Arria 10 FPGA, which is 14X and 1.2X improvement over an Intel Xeon E5 CPU and an Nvidia K80 GPU, respectively.

The streaming applications efficiently and High-level synthesis (HLS) tools allow people without complex hardware design knowledge to evaluate an application on FPGAs, there is an opportunity and a need to understand where OpenCL and FPGA can play in the streaming domains. To this end, we evaluate the overhead of the OpenCL infrastructure on the Nallatech 385A FPGA board that features an Arria 10 GX1150 FPGA. Then we explore the implementation space and discuss the performance optimization techniques for the streaming kernels using the OpenCL-to-FPGA HLS tool. On the target platform, the infrastructure overhead requires 12% of the FPGA memory and logic resources. The latency of the single work-item kernel execution is 11 us and the maximum frequency of a kernel implementation is around 300 MHz. The experimental results of the streaming kernels show FPGA resources, such as block RAMs and DSPs, can limit the kernel performance before the constraint of memory bandwidth takes effect. Kernel vectorization and compute unit duplication are practical optimization techniques that can improve the kernel performance by a factor of 2 to 10. The combination of the two techniques can achieve the best performance. To improve the performance of compute unit duplication, the local work size needs to be tuned and the optimal value can increase the performance by a factor of 3 to 70 compared to the default value.

Detecting similarities between sequences is an important part of Bioinformatics. In this poster, we explore the use of high-level synthesis tool and a field-programmable gate array (FPGA) for optimizing a sequence alignment algorithm. We demonstrate the optimization techniques to improve the performance of the extended sequence alignment algorithm in the BWA software package, a tool for mapping DNA sequences against a large reference sequence. Applying the optimizations to the algorithm using Xilinx SDAccel OpenCL-to-FPGA tool, we reduce the kernel execution time from 62.8 ms to 0.45 ms while the power consumption is approximately 11 Watts on the ADM-PCIE-8K5 FPGA platform.

Development of applications using OpenCL targeting FPGAs is an emerging approach on heterogeneous computing systems. This paper uses the data unpacking algorithm in Base64 encoding as a case study to present programming and optimization techniques, and experimental results of the OpenCL-based implementations on an FPGA. We explain the algorithm and evaluate the performance of the kernel implementations with Intel's FPGA OpenCL SDK. The experimental results show kernel vectorization and duplication are two optimization techniques that can improve the kernel performance. The performance of kernel duplication is also closely related to the local work size. Our experiment shows 16-lane vectorization increases the bandwidth by a factor of 2 to 10 for large input data sizes. Moreover, the performance of kernel duplication using 16 compute units is 40% to 1.5% less than that of kernel vectorization depending on the input size. Tuning the local work size can improve the kernel performance by a factor of 3 to 23. For this kernel, using local memory is not an effective technique to improve the kernel performance because input data is not reused. A combination of vectorization and duplication achieves the highest performance of 12.3 GiB/s. Compared to an Intel Xeon E5 CPU and an Nvidia Tesla K80 GPU, the performance of the kernel on the Arria 10 FPGA is 6.7X faster than the CPU and 3X slower than the GPU. The performance per watt on the FPGA is 20.5X higher than the CPU and 1.19X lower than the GPU.

DC distribution is now becoming the major trend of future mobile power systems, such as more-electric aircrafts and ships. As dc distribution has different nature to the conventional ac system, a new design of well-structured control and management methods will be mandatory. In this paper, a shipboard power system with dc distribution and energy storage system (ESS) is picked as the study case. To meet the requirement of control and management of such a large-scale mobile power system, a hierarchical control design is proposed in this paper. In order to fully exploit the benefit of the ESS, as well as to overcome the limitation in controllability, a novel inverse-droop control method is proposed, in which the power sharing is according to the source characteristic, instead of their power rating. A frequency-division method is also proposed as an extension to the inverse-droop method for enabling a hybrid ESS and its autonomous operation. On the basis of the proposed methods, the control methods for management and voltage restoration levels are also proposed to establish a comprehensive control solution. Real-time simulations are carried out to validate the performance of the proposed control design under different operating conditions. When compared to more conventional droop-based approaches, the new proposal shows enhancement in efficiency.

DC distribution technology has become the new choice and the trending technology of shipboard power systems for its advancement over its AC counterpart. In DC shipboard power systems, the bus voltage stability is a critical issue. The presence of tightly controlled high-power constant power load can induce system-level voltage instability. To mitigate such a problem, a novel compensation method based on model-derived specially designed negative virtual inductance loop is proposed in this paper. The mechanism of the proposed method is presented in detail. In addition to that, the proposed compensation method is compliable with both voltage-controlled and droop-controlled converters. Simulations are carried out to validate the proposed method, and the results show enhanced stability margin and capability when feeding constant power loads.

Recently, DC distribution has been more and more considered in shipbuilding industry as an emerging solution due to its potential to enhance the system performance in terms of fuel economy, reliability, volume and weight. Moreover, there is a growing trend to integrate alternative power sources (APSs) and energy storage systems (ESSs) into next-generation ships, and thus reducing cost and emission. In this context, the future shipboard power systems (SPSs) are expected to be compatible with various generation methods and complex onboard power consumers, which can be naturally identified as islanding microgrids (MGs). In this paper, specialized hierarchical control strategy is proposed to coordinate the system operation and meet the requirement of shipboard applications. Several advantageous functions are achieved by proposed control strategy. A study case of DC SPS is modeled and simulations are carried out to verify the proposed control strategy.

Massively parallel memory systems are designed to deliver high bandwidth at relatively low clock speed for memory-intensive applications implemented on programmable logic. For example, the Convey HC-1 provides 1,024 DRAM banks to each of four FPGAs through a full crossbar, presenting a peak bandwidth of 76.8GB/s to the user logic. Such highly parallel memory systems suffer from high latency, and their effective bandwidth is highly sensitive to access ordering. To achieve high performance, the user must use a customized memory interface that combines scheduling, latency hiding, and data reuse. In this article, we describe the design of a custom memory interface for 3D stencil kernels on the Convey HC-1 that incorporates these features. Experimental results show that the proposed memory interface achieves a speedup in runtime of 2.2 for 6-point stencil and 9.5 for 27-point stencil when compared to a naive memory interface.

In this paper we describe a technique for scheduling memory accesses to improve effective memory bandwidth on the Convey HC-1 platform.

BACKGROUND: Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein's pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein's pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple Field Programmable Gate Array (FPGA)-based platform called the Convey HC-1. RESULTS: The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform's peak memory bandwidth and the implementation's memory efficiency, as 2.03 × peak bandwidth × memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a ~40X speedup when compared with BEAGLE's CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE's GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. CONCLUSIONS: The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design methodology that emphasizes high memory efficiency. To achieve this objective, we integrated 32 pipelined processing elements (PEs) across four FPGAs. For the design of each PE, we developed a specialized synthesis tool to generate a floating-point pipeline with resource and throughput constraints to match the target platform. We have found that using low-latency floating-point operators can significantly reduce FPGA area and still meet timing requirement on the target platform. We found that this design methodology can achieve performance that exceeds that of a GPU-based coprocessor.

In this article we describe a Field Programmable Gate Array (FPGA)-based coprocessor architecture for Frequent Itemset Mining (FIM). FIM is a common data mining task used to find frequently occurring subsets amongst a database of sets. FIM is a nonnumerical, data intensive computation and is used in machine learning and computational biology. FIM is particularly expensive---in terms of execution time and memory---when performed on large and/or sparse databases or when applied using a low appearance frequency threshold. Because of this, the development of increasingly efficient FIM algorithms and their mapping to parallel architectures is an active field. Previous attempts to accelerate FIM using FPGAs have relied on performance-limiting strategies such as iterative database loading and runtime logic unit reconfiguration. In this article, we present a novel architecture to implement Eclat, a well-known FIM algorithm. Unlike previous efforts, our technique does not impose limits on the maximum set size as a function of available FPGA logic resources and our design scales well to multiple FPGAs. In addition to a novel hardware design, we also present a corresponding compression scheme for intermediate results that are stored in on-chip memory. On a four-FPGA board, experimental results show up to 68X speedup compared to a highly optimized software implementation.