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Neal Margulis

dblp:125/2413 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1989
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 67% Integrated circuit design · 33%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture › instruction set architecture › RISC
RISC processor
0.011989
The i860TM 64-bit supercomputing microprocessor · SC 1989
Processor architecture and microarchitecture › superscalar processor
superscalar pipeline
0.011989
The i860TM 64-bit supercomputing microprocessor · SC 1989
YearPublicationVenuePosition
1989 The i860TM 64-bit supercomputing microprocessor
abstract
The Intel i860TM processor is a RISC-based microprocessor incorporating a RISC core with memory management, a floating point unit, and caches on a single chip. The 1,000,000 transistors allow a single chip implementation with highly optimized interunit communication and wide internal data buses. The parallelism and pipelining between the execution units, and the innovative cache management techniques are under explicit control of software. Vectorizable applications can use the pipelined adder and multiplier units to achieve up to 80 Mflops at 40 Mhz for the inner loops of common calculations. Special instructions allow using the data cache as a flexible vector register and support high data bandwidth from main memory. Finally, to support visualization of data, special hardware for 3D graphics is included.
Leslie Kohn, Neal Margulis
SC2