This paper proposes a direct RF baud clock recovery methodology for low-cost energy-efficient real-time demodulations. A baud clock phase-locked loop (PLL) is proposed to directly extract the baud clock from modulated millimeter-wave signals, which employs a type-I PLL incorporating a baud clock phase detector (BCPD). The BCPD uses a super-regenerative sample-and-hold amplifier (SR-SHA) as a RF sampler and extracts the phase misalignments based on DC components of mixing results between input signals and reconstructed samples. To verify the proposed methodology, a prototype of baud clock recovery circuit with a carrier frequency of 60 GHz was implemented in a 40-nm CMOS process. On-wafer measurement results show that the prototype achieves a baud clock recovery speed of 3.65 Gbaud with an RMS jitter below 0.02 unit interval, demonstrating the ability to provide baud clock recovery for BPSK to 1024-QAM demodulation with a low power consumption of 20.2 mW. By eliminating the needs of oversampling and complex digital signal processing in real-time communications, the proposed methodology provides an energy-efficient and low-cost baud clock recovery solution compared to DSP-based approaches.

This paper presents a fully integrated NMOS stimulator using a hybrid dynamic bulk biasing technique (HDBT) and a charge-pump-like control technique (CCT) in a 180-nm bulk CMOS technology. HDBT integrates terminal-voltage-dependent and logic dynamic bulk biasing to set the bulk bias voltage according to the electrode voltage. CCT adds a DC voltage to the gate terminal through a diode and capacitor to help turn on the NMOS transistor. It helps turn off the transistor by shorting the source and gate terminals together and applying two diodes across the drain and source terminals. To achieve an electrode voltage higher than the breakdown voltage of substrate diode ($V_{\mathrm {BD}}$) with an independent power supply, a high voltage tolerant switch is proposed with HDBT and CCT. A high voltage interface is also proposed, utilizing the capacitor adaptive biasing, to overcome the limitation of$V_{\mathrm {BD}}$between the high and low voltage domains and to accommodate the variation of electrode voltage. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves a maximum electrode voltage ($V_{\mathrm {E,MAX}}$) of 18.74V under a 3.3-V supply, with a highest$V_{\mathrm {E,MAX}}$/$V_{\mathrm {BD}}$ratio of 1.27 than state-of-the-art stimulators, including non-standard technology designs. In a continuous output test mode over 10million cycles, the variation of$V_{\mathrm {E,MAX}}$is less than 150mV. The measured maximum residual voltage on the capacitor is 13.55mV.

The article presents a 220GHz terahertz (THz) mixer based on a 130nm SiGe process. This mixer utilizes a Gilbert double-balanced mixer topology and employs a cross-coupled structure with asymmetric capacitive compensation to optimize the layout, enhancing LO-RF isolation. The local oscillator (LO) and radio frequency (RF) ports of the mixer are connected to a driver amplifier and an output power amplifier, respectively, achieving an operational frequency range of 210-230GHz, a conversion gain of 13dB, and a maximum output power of 5.7dBm.

An oscillator-based reconfigurable modulator is proposed to support multi-mode and fast modulation. A direct-modulation structure composed of the cross-coupled oscillator with the fast-switched film bulk acoustic resonator (FBAR) is used to enhance the frequency stability under fast OOK/BFSK modulation. To avoid extra phase-reversal circuitry, a polarity-swapped switching structure is employed in the differential branches of the modulator to achieve energy-efficient BPSK modulation, and this structure is also reused as a buffer stage for OOK/BFSK modulation to avoid the loading effect. In addition, an adaptive fast-switching technique is also proposed to improve OOK/BFSK modulation data rate and energy efficiency. The modulator is fabricated in a 180 nm CMOS technology. The free-running oscillation frequencies with two FBARs are 962 MHz and 990 MHz, and the measured phase noises are -137.3 dBc/Hz@1MHz and -137.1 dBc/Hz@1MHz, respectively. For OOK/BFSK/BPSK modulation, the proposed modulator demonstrated 280/325/67.6 pJ/bit energy efficiency and 5.63/4.20/5.55 % rms EVM with 10/10/50 Mbps data rates.

Super-regenerative receivers (SRRs) hold great promise as a low-cost solution for wireless communication due to their low power and relative simplicity. However, previous researches have primarily concentrated on super-regenerative amplifiers/oscillators, leading to limited insights into SRRs with inappropriate assumptions or dispensable operations, such as synchronous quench and baseband oversampling. This paper presents an improved general theory of super-regenerative reception in the linear mode that provides more design insights for digital communication. By analyzing the time-domain model of a general super-regenerative circuit, we derived a comprehensive frequency-domain model based on a convolution method, through which a concept of signal-lobe transfer function is introduced. Based on the proposed model, the effects of quench jitter and residual phenomenon are analyzed. Furthermore, an asynchronous quench method is introduced, which eliminates the requirement of synchronization between the modulated symbol and the quench signal, thus reducing the system complexity. To eliminate the baseband oversampling, especially for high-speed communications, main-lobe filtering and sub-sampling techniques are also proposed. To verify this general theory and proposed techniques, two SRRs with main-lobe filtering and sub-sampling were designed with ideal components and simulated using Cadence Virtuoso. The simulation results of two SRRs match with the proposed model very well. Overall, this paper provides a comprehensive analysis of super-regenerative reception for digital communication and offers valuable insights into its potentials and limitations.

This paper presents a design methodology for a Class-E inverter with adjustable load-independent (LI) constant current (CC) or LI constant voltage (CV) output, which is applied in battery management devices. The CC/CV output is achieved by setting the power switch to operate at two different frequencies; the two switching frequencies are determined according to the resonant frequency of the multi-resonant network. Following time-domain and frequency-domain design approaches together, the output power and the circuit parameters can be designed at different switching duty cycles, and zero voltage switching (ZVS) is maintained as well. A 6.72MHz/8.1MHz, 12V input,$4.5\sim 18.3$W output prototype is designed and demonstrated to verify the proposed design methodology.

This article presents a Gm-controlled inverter (GC-INV) based amplifier with multiple common-mode feedback (CMFB) loops for multi-channel bio-signal recording. The GC-INV forms a DC-coupled input to ensure a high input impedance. The multi-CMFB, including twin local (TL), regional system (RS), and averaged system (AS) CMFB loops, is introduced through the paralleled GC terminals to provide multiple feedback paths. The TL-CMFB with capacitor-reused topology not only reduces the die area and increases the differential-mode gain, but also reduces the common-mode (CM) gain. The RS-CMFB mitigates the common-mode interference (CMI) due to the mismatch of the CM feedback paths. The AS-CMFB further mitigates the accumulated CMI from CM sampling paths. These CMFB loops avoid the design trade-off between the intrinsic CMRR and the efficiency of area and power. The proposed GC-INV based amplifier with multi-CMFB is fabricated in a 0.18-$\mu $m CMOS technology. It achieves an intrinsic CMRR of 97 dB, TCMRR of 78 dB, and the single-channel INV consumes a chip area of 0.008 mm2.

This brief presents a novel CMOS compact, low-loss digital attenuator chip for low-power, scalable phased array systems. To achieve low-loss amplitude control at high-millimeter-wave (mmW) frequencies with minimal area overhead, the proposed design employs a novel series triple coupled transformer (STCT) structure, integrated with an impedance-tunable network (ITN) to enable multibit control within a compact footprint. Fabricated using a 65-nm-bulk CMOS technology, the 5-bit attenuator chip demonstrates an insertion loss (IL) as low as 3.3 dB across the 110–130 GHz with a 0.5-dB step resolution and an amplitude control range of 15.5 dB. The measured rms amplitude and phase errors are minimized to 0.4 dB and 5.2°, respectively. The core area of the chip is only 0.06 mm2.

This paper presents a fully integrated stimulator using a dynamic bulk biasing technique and a dynamic control scheme in a 180-nm bulk CMOS technology. Unlike the conventional bulk biasing method, the bulk bias voltage is dynamically set according to the different stimulation phases. It avoids the underlying leakage current paths, and improves the maximum stimulation voltage compliance (MSVC). Together with dynamic bulk biasing scheme, a high voltage interface is designed to overcome the limitation of the breakdown voltage of the substrate diode ( V$_{\mathbf{BD}}$) between the high and low voltage domains. An all-NMOS dynamic charge pump is also proposed as a dynamic power supply above V$_{\mathbf{BD}}$and provides dynamic bulk-biasing voltages. Fabricated in a 180-nm standard CMOS technology, the stimulator achieves an MSVC of$\pm$16.5 V under a 3.3-V supply, and the achieved MSVC is$\sim$1.11 times higher than the V$_{\mathbf{BD}}$($\sim$14.8 V) of the substrate diode. The stimulator is also measured in a continuous output test mode for over 10 million cycles, the variation of$\vert$MSVC$\vert$is less than 200 mV.

This brief proposes a parallel multiresidual (PMR) integrator to enhance the noise-shaping (NS) effect for successive approximation register (SAR) analog-to-digital converter (ADC). The PMR employs passive integrators in parallel to simultaneously integrate the average result of the multiple sequential residual voltages. The proposed PMR technique provides an alternative scheme to enhance the NS rather than increasing the order of the integrator to suppress the instability and power. A prototype 7-bit second-order NS-SAR ADC is designed and simulated in a 130-nm CMOS process. PMR increases the effective number of bits (ENOBs) to 10.6 bit, which enhances the NS effect of 3.6 bit. It achieves a peak signal-to-noise and distortion ratio (SNDR) of 65.84 dB over a bandwidth of 1.3 kHz at the oversampling ratio (OSR) of 16.

To further improve the short-term forecasting ability of the critical frequency of the ionosphere F2 layer (foF2), a sample entropy optimized deep learning long-short-term memory (LSTM) forecasting model based on improved complete ensemble empirical mode decomposition with adaptive noise (ICEEMDAN) is proposed. The ICEEMDAN-LSTM model uses the foF2 hour-level time series data of Dourbes station from 2009 to 2019 for training and verification and realizes a single-step high-precision foF2 time series forecast. Through the statistical analysis of the observation of foF2 parameters and the forecast results of the model, the ICEEMDAN-LSTM model can predict foF2 parameters well during the geomagnetic calm and storm periods. Moreover, the proposed model outperforms others in predicting foF2 time series under diurnal and seasonal variation. In the high solar activity year, the RMSE, RRMSE, MAE, and R2evaluation indexes of the ICEEMDAN-LSTM model are 0.19MHz, 4.33%, 0.13MHz, and 0.99, respectively, and they are 0.22MHz, 5.54%, 0.14MHz, and 0.95 in the low solar activity year. The ICEEMDAN-LSTM has the highest forecast accuracy in different solar activity years and is almost unaffected by solar activity. Meanwhile, the prediction performance of ICEEMDAN-LSTM is also verified by observatories in other regions, with high forecasting accuracy. The above shows that the ICEEMDAN-LSTM model has good applicability and usability, and the forecast accuracy of foF2 short-term forecasting can be improved further.

This paper presents a 21.5-to-36 GHz 6-bit radio-frequency variable gain amplifier (RF-VGA) for the fifth generation (5G) communication phased-arrays in 0.13-$\mu$m SiGe BiCMOS technology. To maintain a wideband stable power gain and accurate gain control under all operation states, the two-stage amplifier comprising a cascode amplifier with RC compensating network and a common emitter amplifier is designed and realized. The measured results reveal a wide gain tuning range of-16 to 16 dB, a gain resolution of 0.5 dB with 6-bit digital control, a minimum RMS gain error of 0.04 dB only, 3-dB bandwidth of 13.5 GHz, output $\mathrm{P}_{\mathrm{ldB}}$ compression point of 9.3 dBm, and total DC power consumption of 23.5 mW under 1. 6V supply. The chip area is 0.64×0.4mm2, excluding the testing pads. To the best of the authors’ knowledge, it achieves the best FOM among similar reported VGAs.

This paper presents the design of a compact 60-GHz phase shifter that provides a 5-bit digital phase control and 360° phase range for beam-forming systems. The phase shifter is designed using the proposed cross-coupled bridged T-type topology and switched-varactor reflective-type topology. The topologies are analyzed using a small-signal equivalent circuit model. Furthermore, the design equations are derived and investigated. To validate the theoretical analysis, 60-GHz 5-bit 360° phase shifters are designed in a commercial 65-nm CMOS technology. The fabricated 360° phase shifter features good performance of 32 phase states from 57 to 64 GHz with an rms phase error of 4.4°, a total insertion loss of 14.3 ± 2 dB, an rms gain error of 0.5 dB, P1dB of better than 9.5 dBm, and the power consumption of almost zero. To the best of our knowledge, the designed 360° phase shifter with the size of 0.094 mm2is the smallest 5-bit passive phase shifter at frequencies around 60 GHz.