Modern publish-subscribe systems are increasingly deployed in applications such as smart grids, industrial IoT, and smart homes, where brokers perform not only message forwarding but also in-broker computation. This shift from receive-forward (RF) to receive-compute-forward (RCF) models introduces new privacy and trust concerns, as centralized brokers gain access to sensitive data. In this article, we present a distributed and privacy-preserving RCF ( \(\textsf{DRCF}\) ) framework that replaces the trust assumption on a single centralized broker with multiple semi-honest brokers. Our system integrates distributed authenticated encryption, threshold signatures, and 2-party secure computation realized using homomorphic encryption and garbled circuits to protect both communication and computation. We formally prove the security of \(\textsf{DRCF}\) in the semi-honest adversarial model. We implement \(\textsf{DRCF}\) on top of the Mosquitto broker and evaluate it on real-world IoT workloads, including anomaly detection, load forecasting, and electricity price prediction. Experimental results demonstrate that \(\textsf{DRCF}\) achieves scalability and efficiency while preserving privacy, confidentiality, and integrity in modern publish-subscribe systems.

Electric Vehicles (EVs) are considered the predominant method of decreasing fossil fuels as well as greenhouse gas emissions. With the drastic growth of EVs, the future smart grid is expected to extensively incorporate dynamic wireless charging (DWC) systems, a significant advancement over traditional charging methods. DWC, offering the unique ability to charge vehicles in motion, introduces new infrastructures, complex network models and consequently, a massive attack surface. To accomplish the goal of such an enormous smart grid accompanying DWCs, the security of EV charging infrastructures has become a deciding factor. EV charging is vulnerable to cyberattacks as it has many attack vectors and many challenges to combat. Unlike the traditional charging services provided in a typical static charging station, the DWC has a complex network architecture which makes it vulnerable to many forms of cyberattacks. Authentication plays a crucial role in safeguarding the frontline security of this ecosystem. However, within the domain of DWC, the current academic landscape has seen limited attention dedicated to authentication protocols. This background signifies the necessity of a comprehensive survey to cover the authentication protocols of dynamic wireless EV charging environments. This review paper examines the security requirements and the network model of the DWC, providing comprehensive insights into existing authentication protocols by scrutinizing a proper classification. Furthermore, the paper addresses existing challenges in authentication schemes within DWC and explores potential future research tendencies aiming to strengthen the security framework of this emerging technology.

A binary de Bruijn sequence is a sequence of period 2n in which every binary n-tuple occurs exactly once in each period. A de Bruijn sequence has good randomness properties, such as long period, ideal tuple distribution, and high linear complexity, and can be generated by a nonlinear feedback shift register (NLFSR). Finding an efficient NLFSR that can generate a de Bruijn sequence with a long period is a significant challenge. “Composited construction” is a technique for constructing a de Bruijn sequence of period 2n+kby an NLFSR from a de Bruijn sequence of period 2nthrough a composition operation repeatedly applying k times. The goal of this article is to further investigate the composited construction of de Bruijn sequences with efficient hardware implementations, and determine randomness properties such as linear complexity. Our contributions in this article are as follows. First, we present a generalized construction of composited de Bruijn sequences that is constructed by adding a combination of conjugate pairs of different lengths in the feedback function of the composited construction, which results in generating a class of de Bruijn sequences of size 2k, whereas the original composited construction can generate only two sequences. Second, we investigate the linear complexity and the correlation property of the new class of de Bruijn sequences. We prove theoretically that the linear complexity of this class of de Bruijn sequences is optimal or close to optimal. Interestingly, we also prove that the linear complexities of all the sequences of this class are equal, which strengthens Etzion's conjecture (JCTA 1985, IEEE-IT 1999) about the number of de Bruijn sequences with equal linear complexity. This is the first known construction of de Bruijn sequences of an arbitrarily long period whose linear complexities are determined theoretically. Finally, we implement our construction in hardware to demonstrate its practicality. We synthesize our implementations for a 65 nm ASIC and a Xilinx Spartan FPGA and present hardware areas, and performances of de Bruijn sequences of periods in the range of 2160to 21056. For instance, a class of de Bruijn sequences of period 2160(resp. 2288) can be implemented with an area of 3.43 (resp. 6.71) kGEs in 65 nm ASIC, and 83 (resp. 229) slices in Spartan6 FPGA.

The security of highly resource constrained applications is often viewed in the literature from a single aspect of a specific cryptographic primitive. More precisely, most of the proposed lightweight cryptographic primitives focus on providing a single functionality within the available hardware area dedicated for security purposes. In this paper, we argue that for such applications, a cryptographic primitive that follows the cryptographic minimal design strategy maybe the only realistically adopted security solution where there is a constrained GE budget for all security functionalities. Indeed, it is reasonable, if not desirable, for the adopted cryptographic design to have well justified building components and to provide minimal overhead for multiple cryptographic functionalities including encryption, hashing, authentication, and pseudorandom bit generation. Following such a strategy, we propose the sLiSCP family of lightweight cryptographic permutations which employs two of the most hardware efficient and extensively cryptanalyzed constructions, namely a 4-subblock Type-2 Generalized Feistel-like Structure (GFS) and round-reduced unkeyed Simeck. In addition to the hardware efficiency, we follow restrictive security design goals which enable us to provide resistance against differential and linear cryptanalysis, as well as guaranteed resistance to diffusion-based, algebraic, and self-symmetry distinguishers, and accordingly, we claim that there exist no structural distinguishers for sLiSCP-b with a complexity below 2b=2 where b is the state size. Moreover, we present the sLiSCP duplex sponge mode to illustrate how the permutations can be used in a unified design that provides (authenticated) encryption, hashing, and pseudorandom bit generation functionalities. Finally, we report two efficient parallel hardware implementations for the sLiSCP unified duplex sponge mode when using sLiSCP-192 (resp. sLiSCP-256) in CMOS 65 nm ASIC with area of 2289 (resp. 3039) GE and a throughput of 29.62 (resp. 44.44) kbps, and their areas in CMOS 130 nm are 2498 (resp. 3319) GE.

The emerging areas in which highly resource constrained devices are interacting wirelessly to accomplish tasks have led manufacturers to embed communication systems in them. Tiny low-end devices such as sensor networks nodes and Radio Frequency Identification (RFID) tags are of particular importance due to their vulnerability to security attacks, which makes protecting their communication privacy and authenticity an essential matter. In this work, we present a lightweight do-it-all cryptographic design that offers the basic underlying functionalities to secure embedded communication systems in tiny devices. Specifically, we revisit the design approach of the sLiSCP family of lightweight cryptographic permutations, which was proposed in SAC 2017. sLiSCP is designed to be used in a unified duplex sponge construction to provide minimal overhead for multiple cryptographic functionalities within one hardware design. The design of sLiSCP follows a 4-subblock Type-2 Generalized Feistel-like Structure (GFS) with unkeyed round-reduced Simeck as the round function, which are extremely efficient building blocks in terms of their hardware area requirements. In S L I SCP-light, we tweak the GFS design and turn it into an elegant Partial Substitution-Permutation Network construction, which further reduces the hardware areas of the S L I SCP permutations by around 16% of their original values. The new design also enhances the bit diffusion and algebraic properties of the permutations and enables us to reduce the number of steps, thus achieving a better throughput in both the hashing and authentication modes. We perform a thorough security analysis of the new design with respect to its diffusion, differential and linear, and algebraic properties. For S L I SCP-light-192, we report parallel implementation hardware areas of 1,820 (respectively, 1,892)GE in CMOS 65 nm (respectively, 130 nm ) ASIC. The areas for S L I SCP-light-256 are 2,397 and 2,500GE in CMOS 65 nm and 130 nm ASIC, respectively. Overall, the unified duplex sponge mode of S L I SCP-light-192, which provides (authenticated) encryption and hashing functionalities, satisfies the area (1,958GE), power (3.97μ W ), and throughput (44.4kbps) requirements of passive RFID tags.

A binary de Bruijn sequence with period 2nis a sequence in which every tuple of n bits occurs exactly once. De Bruijn sequence generators have randomness properties that make them attractive for pseudorandom number generators and as building blocks for stream ciphers. Unfortunately, it is very difficult to find de Bruijn sequence generators with long periods (e.g., 2128) and most known de Bruijn sequence generators are computationally quite expensive. In this article, we present “OcDeb-k-n” and the first hardware implementation of de Bruijn sequence generators. OcDeb-k-n efficiently computes a composited de Bruijn sequence where k levels of composition are added to a de Bruijn sequence of period 2n. Numerically, OcDeb reduces the bit operations used for computing the feedback function significantly from Θ(k2+ nk) to Θ(k log k + logn). Furthermore, it enables efficient parallelization and hardware retiming. Comprehensive result analysis is conducted for 65 nm ASIC technology. For example, OcDeb-32-32 has an area of 643 GE with 1.45 Gbps performance, and with parallelization it generates up to 25.4 Gbps at the cost of 4,787 GE. The area of OcDeb-512-32 generating a de Bruijn sequence of period 2544is 7,304 GE and the performance is 1.25 Gbps.

A binary de Bruijn sequence of order$n$is a sequence of zeros and ones of period$2^n$that contains every binary$n$-tuple exactly once in a period of the sequence. A composited construction of a de Bruijn sequence is a construction of a nonlinear feedback shift register (NLFSR) that generates a de Bruijn sequence where the composited feedback function of the NLFSR is the sum of a feedback function with$k$th order composition and a sum of$(k+1)$product-of-sum terms. The goals of this article are to perform a profound analysis of composited de Bruijn sequences for use in cryptography and find an efficient implementation of the composited feedback function. We first determine the lower bound of the linear complexity of a composited de Bruijn sequence and then conduct a profound analysis on the composited construction by introducing the notion of the higher order$D$-morphic preimages of a binary sequence. Our analysis aims at the reconstruction of a composited de Bruijn sequence from a segment known as$k$th order$D$-morphic order$n$de Bruijn preimages ($(n,k)$-DMDPs) of length$(2^n+k)$and$k$th order$D$-morphic order$n$$m$-sequence preimages ($(n,k)$-DMMPs) of length$(2n+k)$for a nonlinearly and linearly generated composited de Bruijn sequence, respectively. We also provide the success probability of finding an$(n,k)$-DMMP/DMDP from a composited de Bruijn sequence for the reconstruction. Furthermore, we develop a new iterative technique with its parallel extension for computing the feedback function and the new technique is faster than other known techniques for producing de Bruijn sequences of long period. In addition, we present three instances of composited de Bruijn sequences of period$2^{64}$together with their software implementations and performances.

With the advent of ubiquitous computing and the Internet of Things (IoT), the security and privacy issues for various smart devices such as radio-frequency identification (RFID) tags and wireless sensor nodes are receiving increased attention from academia and industry. A number of lightweight cryptographic primitives have been proposed to provide security services for resource-constrained smart devices. As one of the core primitives, a cryptographically secure pseudorandom number generator (PRNG) plays an important role for lightweight embedded applications. The most existing PRNGs proposed for smart devices employ true random number generators as a component, which generally incur significant power consumption and gate count in hardware. In this article, we present Warbler family, a new pseudorandom number generator family based on nonlinear feedback shift registers (NLFSRs) with desirable randomness properties. The design of the Warbler family is based on the combination of modified de Bruijn blocks together with a nonlinear feedback Welch-Gong (WG) sequence generator, which enables us to precisely characterize the randomness properties and to flexibly adjust the security level of the resulting PRNG. Some criteria for selecting parameters of the Warbler family are proposed to offer the maximum level of security. Two instances of the Warbler family are also described, which feature two different security levels and are dedicated to EPC C1 Gen2 RFID tags and wireless sensor nodes, respectively. The security analysis shows that the proposed instances not only can pass the cryptographic statistical tests recommended by the EPC C1 Gen2 standard and NIST but also are resistant to the cryptanalytic attacks such as algebraic attacks, cube attacks, time-memory-data tradeoff attacks, Mihaljević et al.’s attacks, and weak internal state and fault injection attacks. Our ASIC implementations using a 65nm CMOS process demonstrate that the proposed two lightweight instances of the Warbler family can achieve good performance in terms of speed and area and provide ideal solutions for securing low-cost smart devices.

This paper presents a novel method for solving channel assignment problems (CAPs) in hexagonal cellular networks with nonhomogeneous demands in a 2-band buffering system (where channel interference does not extend beyond two cells). The CAP with nonhomogeneous demand is first partitioned into a sequence of smaller subproblems, each of which has a homogeneous demand from a subset of the nodes of the original network. Solution to such a subproblem constitutes an assignment phase, where multiple homogeneous demands are assigned to the nodes corresponding to the subproblem, satisfying all the frequency separation constraints. The whole assignment process for the original network consists of a succession of multiple homogeneous assignments for all the subproblems. Based on this concept, we present a polynomial time approximation algorithm for solving the CAP for cellular networks having nonhomogeneous demands. Our proposed assignment algorithm, when executed on well-known benchmark instances, comes up with an assignment which is always within about 6 percent more than the optimal bandwidth, but requires a very small execution time (less than 5 millisecond on a HPxw8400 workstation). The proposed algorithm is very much suitable for real-life situations, where fast channel assignment is of primary importance, tolerating, however, a marginal deviation (6 percent) from the optimal bandwidth.