In data-parallel computing that uses a graphic processing unit (GPU), processing of large data requires that multiple GPUs be used in the computer to increase its execution performance. Increasing processing performance by using multiple computing resources has been enabled by the development of computing frameworks based on a directed acyclic graph (DAG). However, their performance degrades in out-of-core processing, which often occurs in processing of large data on GPUs with limited memory capacity. The GPU data input/output (I/O) for data swapping between host memory and GPU memory during the execution of a user DAG is usually a performance bottleneck. A computing framework called "Victream" is proposed to overcome this drawback. It uses a novel scheduler that involves two methods to minimize the total amount of GPU data I/O of data swapping. First, it performs locality-aware scheduling. When it schedules a task, it selects one that requires the minimum amount of data swapping and reuses as much of the data residing in GPU memory as possible. Second, it extends the locality-aware scheduling so that GPUs can execute data prefetching. Prefetching data that are swapped out from a GPU enables efficient use of bottleneck GPU I/O resources. To prefetch the input data of future tasks, it is required to determine the schedule of future tasks. Victream's scheduler (hereafter, the Victream scheduler) extends the locality-aware scheduling so that it can schedule future tasks to enable data prefetching that is executed in the way that minimizes the amount of data I/O of data swapping. Evaluation of a Victream prototype showed that the performance of Victream is better than that of conventional frameworks by up to 117%.

Networked devices in an Internet-of-Things (IoT) environment generally need to be controlled or organized by a central controlling host. These IoT devices are implemented together with a small computer that consists of a central processing unit (CPU), a memory, and input/output (I/O) devices to communicate with this host. The small computer uses its own software network stack for communication. This paper reports our study of another finer-grained IoT in which an IoT device is not implemented with a computer but just an I/O device. The I/O device works as the local device of a remote controlling host and the IoT device is controlled by data communication with the controlling host through the I/O device. Such an IoT system simplifies the internal configuration of an IoT device node and can lower its implementation costs. However, previous methods have required a special hardware interface to their controlling host to connect to a remote I/O device that is implemented together with an IoT device. This paper proposes a novel software virtualization architecture for a controlling host to connect to I/O devices distributed in an Ethernet. It virtualizes a remote I/O device that communicates through the standard network interface card (NIC) of a host as an I/O device that is contained in the I/O device tree of the host. Various kinds of computers ranging from hand-held to rackmount ones are enabled to control remote IoT devices with the installation of the proposed software. In addition, because virtualization is performed in the PCI Express (PCIe) layer, any complying I/O device is remotely interconnected and is driven by its device driver without modifications. The feasibility of the method was studied by evaluating the implemented prototype using a NIC and a storage controller.

Extending input/output (I/O) bus networks over wireless Ethernet is expected to provide an effective way of achieving communication between multiple hosts and I/O devices. However, because connections on wireless Ethernet are lossy and unreliable, retransmission of I/O packets increases transmission latency that exceeds the limits of the I/O bus protocol. In this paper, we propose an Ethernet transport mechanism that adopts rateless codes to provide reliable transmission without having to retransmit packets. We further devised a queuing model to set the operating parameters of rateless codes to bound the probability of end-to-end latency that exceeds the defined limit value. Our results obtained through simulations and an FPGA implementation show that the proposed method decreased the transmission latency of I/O packets and enabled it to meet the requirements of the I/O bus protocol.

Input/output (I/O) devices such as a graphics processing unit and a solid-state drive are inserted into I/O slots of a host in data center platforms. With this sort of configuration the I/O devices are used exclusively by the host with resultant inefficient resource usage. In addition, the maximum number of I/O devices that can be assigned to each host is limited by the number of its I/O slots. This paper proposes a method to solve the resource usage inefficiency and assignment limitation by disaggregating I/O devices from hosts. An I/O device accommodated in a device pool is interconnected with multiple hosts by a standard Ethernet and can be flexibly assigned to one of them. Introducing assignment flexibility of I/O devices among hosts improves the resource usage efficiency and enables as many I/O devices as desired being assigned to each host. The authors further propose a method that enables an I/O device to be simultaneously shared among multiple hosts and multiple I/O packets to be aggregated into an Ethernet frame to suppress the performance overhead of the device disaggregation. Evaluation results showed that I/O devices that are compliant to PCI Express are shared with the overhead up to 27 percent.

The objective of our research has been to achieve energy-saving key-value store system. We introduce architecture of our distributed key value store and control framework for energy saving. To reduce power consumption, the control framework should reduce the time required before node power-down. Since this time depends heavily on the amount of data migration, we employ an approach which reduce that amount. We describe and evaluate three control strategies that can be executed on this control framework, each consisting of a data allocation algorithm and data control layout algorithm for use when nodes are to be powered down. With a prototype system developed for evaluation purposes, the time required before node power down is reduced by use of our proposed data allocation algorithm, by means of its taking into account the possible presence of Write off-loading nodes.