The disturbance of velocity sensor data may cause serious problems when the motor is running at high velocity. To tackle this issue, a velocity estimation method for high-speed linear induction motors (HS-LIM) is proposed in this paper. Firstly, the state equations of voltage, current, and velocity are established in a synchronous coordinate system to obtain the relationship between the voltage and the velocity. Secondly, the voltages of each stator section are used to synthesize the voltage characteristic waves, which are used to calculate the velocity. Finally, two velocity estimation values are fused into one more precise velocity data based on the Kalman filtering recursion algorithm. The simulation experiment verifies that the voltage characteristic waves can accurately estimate the mover velocity of HS-LIM, and the Kalman fusion velocity gets better precise.

The Cascaded H-bridge energy storage converter (CHBESC) integrates energy storage components within cascaded multilevel converters to deliver short-term high power to the stator of ultra-high-speed linear motors. This integration effectively mitigates the impact on the power grid. However, during the acceleration and braking of the ultra-high-speed linear motor, the frequency of the CHBESC output voltage varies with the motor speed. This variation causes the frequency of secondary harmonic currents in the submodules to fluctuate accordingly. To address this issue, this paper establishes an analytical model for secondary harmonic voltage and current over a wide frequency range. The study investigates the fluctuation patterns of these harmonics under different control and circuit parameters, providing theoretical guidance for the design of circuit parameters and controllers. Simulation results validate the accuracy of the model and the effectiveness of the parameter design guidance.

Low switching frequency of power semiconductor devices is expected to decrease losses in the cascaded H-bridge (CHB) inverter with supercapacitor and dc–dc stage. This paper proposes a switching frequency reduction method accompanied by a hybrid modulation strategy (HMS) for the CHB inverter. By optimizing the comparison output between the reference wave and the triangular carrier, unnecessary state jumps in the switching signals for the H-bridge can be avoided when rotating the switching mode of the H-bridge in the HMS. The proposed method can reduce the average switching frequency among the H-bridges without side effects on capacitor voltage balance and ac outputs. Finally, its effectiveness is demonstrated through simulation results of five SMs based on MATLAB/Simulink.

Energy balancing control in cascaded multilevel energy storage inverters (CMESIs), which consist of distributed energy storage devices across power modules (PMs), poses a significant challenge. Existing studies have identified limitations and shortcomings in achieving energy balance through differential power distribution to individual PMs. This paper presents a comparative analysis of two established energy balancing control strategies to assess their respective regulation capabilities for the CMESIs. The effectiveness of the selected strategy is verified through the simulation results, showcasing its potential to achieve energy balance in the CMESIs. The findings contribute to the advancement of energy balancing control techniques, offering valuable insights to enhance system performance and stability in practical applications.

The study focuses on the interphase power imbalance problem in the cascaded multilevel energy storage inverter for ultra-high-speed linear motor propulsion (UHSLMP) systems. The traditional interphase energy balancing methods, which rely on fixed frequency and amplitude, are limited due to the continuous variation of supply voltage amplitude and frequency, traditional zero-sequence voltage injection methods with constant values are inadequate. To address this challenge, this paper analyzes power calculation and definition considering the time-varying AC supply and establishes a phasor model that accounts for the time-varying amplitude and frequency. Based on this model, a novel zero-sequence voltage injection method is proposed to tackle the interphase energy balance problem under varying amplitude and frequency conditions. Simulation results demonstrate the effectiveness of the proposed method.

The nonlinear characteristics of the thyristor and its real-time fault injection problem greatly challenge the hardware-in-the-loop (HIL) implementation of high-speed linear motors (HSLM) with power supply switching faults. In this paper, a real-time simulation model based on the improved associated discrete circuit switch model is proposed by analyzing the operating characteristics of the thyristor in healthy and faulty states. The entire segmented power supply system is constructed on an FPGA-based HIL platform using the fixed-point schematic to verify the correctness of the proposed model. The results of the offline simulation and HIL test demonstrate that the proposed model can precisely reflect the current asymmetry caused by the mutual asymmetry inductance of the stator windings after a power switching fault. The research can provide a test platform for fault diagnosis algorithms and control protection strategies for HSLM with segmented power supply systems.

The high-speed linear induction motor (LIM) has multiple parameters coupling and fast time-varying characteristics, which easily leads to current and thrust control instability and further restricts speed improvement. To address this issue, this paper proposes a decoupling mathematical modelling method to accurately characterize the time-varying parameter feature of LIMs. Subsequently, an indirect magnetic field orientation control strategy, consisting of the voltage feedforward control algorithm and a PID feedback control algorithm with time-varying parameters, is proposed based on the mathematical model. The simulation results demonstrate that the proposed method exhibits better stability in the fast changes of parameters, and the speed of the LIM is superior to the traditional methods.

Hardware-in-the-loop (HIL) real-time simulation of cascaded H-bridge inverter (CHBI) with supercapacitor and DC-DC stage is one of the important links in the development of its controller. This paper presents a full-scale HIL simulator for the CHBI. Firstly, the discrete mathematical model of the CHBI is derived and implemented by utilizing several field programmable gate arrays (FPGAs) as the solving units. Each FPGA is equipped with up to twelve fiber optic communication interfaces, allowing one-to-one connection between the simulator and its controller. The simulation capacity of the presented simulator can be easily expanded through incorporating more FPGAs and combining data communication. Finally, the effectiveness of the presented simulator for the CHBI is verified through the gridconnected charging HIL real-time simulation results.

In the switching process of segmented power supply linear motor (SPSLM), the thyristor can cause the switching current impact and lead to insufficient utilization of converter capacity. To reduce this current impact, the mathematical model of linear motor concerning the parallel connection and zero-state response is deduced, the influence of different voltage switching angles on the current of the converter is analyzed, and then a switching method is proposed by calculating the position of the mover and voltage phase angle to minimize the effect of parallel connection and the zero-state response of stator. The electromagnetic transient simulation is implemented in Matlab/Simulink platform, the simulation results verify that the proposed method can reduce 50% of the current impact by comparing it with the conventional method.

Cascaded H-bridge multilevel converter(CHBC) has become a highly attractive topology in high-voltage and large-capacity energy storage system(ESS). In a cascaded H-bridge multilevel energy storage converter(CHB-ESC), energy storage elements(ESEs) such as batteries and supercapacitors are distributed in each power sub-module(PM), and the energy balancing among the ESEs is of great importance. In a two-stage CHB-ESC, the voltage balancing of the DC-link capacitors and the energy balancing of the ESEs should be met simultaneously. Due to the limitation of the charging and discharging current of the ESEs, the large current on the AC side in high-power applications will cause large ripple on the voltage of the DC-link capacitor. In order to reduce the voltage ripple of the DC-link capacitor in the two-stage topology, this paper proposes a novel voltage balancing method of CHBC with supercapacitors ESS for capacitor voltage ripple reduction. The PMs rotation is realized by a multi-factor weight optimal sorting method based on the voltage value of the supercapacitors and the voltage value of the DC-link capacitors. While ensuring the voltage balancing among the supercapacitors of each PM, the voltage ripple of the DC-link capacitors can be effectively reduced. Finally, the effectiveness of the proposed method is verified by simulation results.

The nonlinear feature of thyristor and asymmetry geometry of multiphase bring the great challenge to achieve real-time modeling of segmented multiphase linear motor (SMLM). In this paper, the physical characteristics of the thyristor and neutral point of the stator are analyzed to propose real-time modeling of SMLM switched by the thyristor. The pipelined and parallel structure of FPGA is introduced to reduce the hardware resource requirement of FPGA and accelerate the simulation speed. The HIL test platform based on Xilinx Virtex 7 series FPGA is built to verify the accuracy and efficiency. The results show that the proposed model can precisely reflect the nonlinear feature of the current zero-crossing shutdown of the thyristor without iteration when turning OFF and the zero-state response of the stator when turning ON. This research can be used for the hardware in the loop test of a high-speed linear motor propulsion system.

Cascaded H-bridge with bidirectional DC-DC converter (CHBDC) is promising in high voltage supercapacitor (SC) energy storage applications, in terms of multilevel voltage output, modularity, high efficiency, etc. However, the charging process becomes complicated when part of the SC voltages reach the target value ahead of the others. The improper charging may cause the CHBDC over-modulation and even grid current distortion. To solve this problem, this paper analyzes the stable operation area of the CHBDC in this scenario. Based on these analysis, a coordinated charging strategy is also proposed for the CHBDC, by adjusting the reference voltage of each H-bridge unit and the grid power factor. Simulation results show the validity of the proposed charging strategy.

A dual active bridge series resonant converter (DABSRC) is proposed with the isolation of an air-core high frequency transformer (ACT) in this paper. It reduces the weight of the transformer without the magnetic core which improves the gravimetric power density of DABSRC. It adopts crossed figure-eight shaped windings to ensure high coupling capability of ACT. In addition, the simplified ACT T-type equivalent model is established. Based on this model, the soft-switching characteristics of DABSRC are also analyzed in this paper. Simulations on a 100 kW 1kV / 750V DABSRC verify the validity of the proposed ACT-DABSRC.

The pulse width modulation current source converter (PWM-CSC) has been regarded as one of many interesting circuit topologies in high-power systems. This paper analyzes the influence of system parameters on the power operating range of PWM-CSC, and designs the parameters for PWM-CSC applied to HVDC transmission system. A 250 kV/500 MW PWM-CSC based HVDC transmission system is built using PSCAD/EMTDC software, and the experimental platform was built to verify the correctness of the analysis and the feasibility of the design.

Due to the existence of tail current of IGBT, dual active bridge series resonant converter (DABSRC) cannot achieve true zero current switching (ZCS). In this paper, the efficiency of the converter is improved by using hybrid switch (HyS) and optimized switching pattern, SiC MOSFET and Si IGBT of the HyS are operated in segments depending on the on-state resistance of the devices, and the conduction loss and switching loss is optimized at the same time. The method proposed is verified by simulation, and the preliminary experiments prove the feasibility of the proposed strategy.

The cascaded H bridge-power electronic transformer (CHB-PET) has potential application in traction and smart grid, however, it is a great challenge to achieve fast electromagnetic transit because of numerous nodes and nonlinear devices and high switching frequency. The equivalent model of the submodule and three-phases CHB-PET with the detailed feature of the high-frequency circuit, which can reduce the size of the admittance matrix, eliminate the affection of switching state to admittance matrix, and alleviate the impact of the increasing number of submodules per arm on computing time, are proposed to speed up simulation of CHB-PET. The accuracy and computing performance are verified by comparison of reference and proposed models in Matlab Simulink. Simulation results show that the proposed model has good performance of accuracy under blocked mode and unlock mode, and has excellent performance of computing time with the increasing of the number of submodules per arm. It can significantly speed up the offline simulation of CHB-PET. Moreover, the proposed model has great potential for real-time simulation by CPU and FPGA hardware platform.

Full-bridge submodule (FBSM) voltage ripples can achieve a significant reduction of FBSM-based modular multilevel converter (FB-MMC) with boosted ac voltages. However, the FBSM voltage ripples increase substantially when single-line-to-ground (SLG) faults occur, which may cause damage to the safe operation of FB-MMC. This paper analyzes the FBSM voltage ripples characterization of the FB-MMC under SLG faults conditions. It is found that the fundamental frequency component, which is minor in steady-state operations, becomes dominant in the event of SLG faults leading to a dramatic increase of FBSM voltage ripples. Based on these analyses, a circulating current injection (CCI) method is proposed in order to suppress the main components of the FBSM fundamental frequency fluctuations. Both of the presented analysis and the effectiveness of the proposed CCI method are verified by simulations on a ±200 kV FB-MMC system.

For medium- to high-voltage ac-ac conversion applications, direct ac-ac modular multilevel converters (MMCs) show advantages on power density compared to indirect ac-ac (ac-dc-ac) MMCs. However, direct ac-ac MMCs suffer from branch energy divergence when the operation frequencies of the input and the output are equal. This paper investigates the three-phase to single-phase direct ac-ac MMC under equal frequency operation condition and proposes a novel control strategy to balance its branches' energies. The effectiveness of the control strategy is validated by the simulation results.

For medium- to high-voltage AC/AC conversion applications, direct AC/AC conversion scheme by adopting the modular multilevel converter (MMC) shows remarkable advantages on costs and efficiency compared with the AC/DC/AC solution which employs a back-to-back MMC configuration. However, direct AC/AC MMC suffers from branch energy instability when conversion frequencies of input and output are equal. This paper presents a sept-branch MMC (SB-MMC) topology for direct AC/AC conversion applications. The feature of this SB-MMC is its capability of direct AC/AC equal frequency conversion from three-phase to single-phase and vice versa. Balanced branch energy and unity power factor at grid side can be achieved simultaneously under various load conditions. Operating principle as well as control strategy of the SB-MMC are described. Simulation on a 27.5kV/50MVA SB-MMC model for railway power supply is carried out. Simulation results validate the effectiveness of the SB-MMC and the proposed control strategy as well.

In this paper, a novel configuration of the back-to-back (BTB) converter interconnecting two synchronous AC grids is proposed. The feature of this BTB converter configuration is the substantially reduced capacity compared with the exchanged power between the two grid partitions. Unlike the conventional full-capacity BTB converters, the capacity of the proposed BTB converter in this paper is around 50% of the exchanged power. Besides, the fault ride-through ability of the proposed converter is also enhanced, compared with the unified power flow controller (UPFC) based active power exchange/control systems. The control strategy of this BTB converter is also presented fulfilling both the active and reactive power requirements, unity power factor (UPF) for instance, of the two AC grids. The characteristics of this converter are also analyzed under and short circuit fault conditions at both sides of the two grids. Simulation results on a 127 kV/108 MW AC grid interconnection system show validity of the proposed converter circuit with the control strategy.

This paper develops an alternate arm converter (AAC) high-voltage direct current (HVDC) terminal model that is compatible with the existing benchmark models of modular multilevel converter (MMC) based HVDC and dc-grid benchmark models. The developed model is a first step towards an AAC-based point-to-point transmission system and the future development of multi-converter, multiterminal benchmark models that facilitate system level studies with multiple topologies. The topology, configuration, design considerations and parameters of the model are derived in order to provide a direct equivalence with the MMC-based system. Detailed simulation studies of the multilevel converter demonstrate the operation and performance of the AAC-based benchmark model and the associated control functions.

This paper proposes a transformer-less modular multilevel DC/DC converter. The proposed converter can be used to interconnect two HVDC systems with different dc voltage levels and realize bidirectional power flow. Based on the arm energy balance condition, the optimal design arming at minimum inner circulating current is presented. A power close-loop control method is adopted to regulate the converter transmission power. In the method, since the ac component of the reference voltage for each arm is high frequency, the volume of sub-module (SM) capacitor is reduced. Finally, a 320 kV/160 kV 80 MW modular multilevel DC/DC converter is built using PSCAD/EMTDC software. The results validate the operation principle of the proposed converter.

Because the numerous nonlinear components and fiber interfaces are used in Module Multiple Converter (MMC), the HIL test of MMC with detailed EMT model and the full-scale interface is hard to be implemented. In recent years, this existing disadvantage caused the MMC controller hardware and software difference between the HIL test and real project. In this paper, a detailed EMT model of hybrid MMC fitting for full-scale interface HIL test is proposed, and the equivalent arm circuit of hybrid MMC and the nonlinear feature of the sub-module are introduced. Then the full-scale interface HIL test system is built to test the performance of proposed model under various conditions. Comparing with the reference model built in MATLAB with detailed semiconductor model, the accuracy of the proposed method can meet the requirement of HIL tests, the current difference of two methods is less than 0.73% and the capacitor voltage difference is less than 0.39%. Due to the full-interface structure, the proposed method can simulate the divergence of capacitor voltage and all faults of the submodule. The MMC controller tested by the proposed method can be directly used in the real project without hardware and software modification.

Modular multilevel converter (MMC) has attracted great attention in the high voltage direct current (HVDC) transmission systems. Redundant submodules (SMs) are usually set to enhance the reliability of MMC. However, if some SMs break down, the arm energy is unbalanced and fundamental fluctuation appears in the DC current. This paper proposes an arm energy rebalancing control scheme to suppress the fluctuation. The proposed scheme does not increase the SM voltage if the fault number is not more than the rated number of redundant SMs, unlike the conventional schemes. Additionally, the average losses of SMs are analyzed respectively, when the proposed and conventional schemes are adopted. The simulation results of the ±350 kV/1000 MW MMC verify the correctness of the proposed energy rebalancing control scheme and its characteristic of low loss in comparison with the conventional schemes.

Hybrid transmission systems associated with line commutated converters (LLC) and voltage source converters (VSC) have gradually become a particular solution for high voltage direct current (HVDC) transmission. The full-bridge submodule (FBSM) based modular multilevel converter (FB-MMC) has gained significant attention for its dc voltage reversal and fault ride through capabilities. However, large capacitance is essential for high power transmission of FB-MMC, increasing cost and size rapidly. This paper analyzes the FBSM voltage fundamental frequency and second-order harmonic fluctuations of the FB-MMC with zero sequence voltage injection. The design principles of the FBSM capacitance are also presented compared with the one without zero sequence voltage injection under equivalent voltage ripple conditions. Finally, comparative simulation results on a FB-MMC system verify the correctness of the analyses.

As the converter exchanging the active powers between AC grids/connection points, electric energy router (EER) gained popularity in grid interconnection, smart grid and energy internet systems. Conventionally, AC/DC with DC/AC i.e. the back-to-back (BTB) converter is the typical choice for EER. However, BTB converters must withstand the high voltage of the AC grid and the power capacity is usually very high. This paper proposes a simple circuit for EER connecting two AC grids or connection points with the same voltage amplitude and phase. This EER can exchange the active power of AC grids by low-voltage converter. Meantime, the power capacity of this EER is much lower than the rating of the exchanged active power. Verification results show validity of the proposed EER circuit.

A control scheme is proposed to optimize the Modular Multilevel Converters (MMC) efficiency based on harmonic circulating current injection. With the presented efficiency optimization scheme, the MMC loss is reduced by about 3% to 4% compared to the conventional circulating current eliminating method under the rated 1000MW. The relationships between the losses and the harmonic circulating currents in MMC are also derived. Verification results show correctness of this control scheme.

Modular Multilevel Converter (MMC) is considered a promising circuit topology for high voltage and high power applications. There is a trade-off between submodule (SM) capacitor voltage balancing and switching frequency. In this paper, an adaptive SM capacitor voltage balancing method is proposed based on that different arm currents have different charging or discharging capabilities. The algorithm can reduce switching frequency without affecting capacitor voltage balancing. The threshold current selection and average switching frequency calculation of power device are presented which provide theoretical basis to system design. Finally, the simulation results validate the effectiveness of the proposed method.