This study developed an application-specific integrated circuit (ASIC) with a speed controller, a nine-stage error fuzzy controller, and a discrete multiple vector voltage (DMVV) system for modified direct torque control (MDTC). By using the nine-stage error fuzzy controller, the proposed system effectively stabilizes a motor’s flux and ensures high control precision by incorporating speed feedback. This feature enables the system to ensure that the flux and torque values are close to the designed values, which results in high motor performance. A DMVV switching table plays a crucial role in facilitating the appropriate six-switch signals on the basis of the modified flux and torque signals from the fuzzy controller. The proposed DMVV system considerably reduces ripples and enhances overall system stability by generating more vector voltages than those generated in the conventional DTC method. The proposed system architecture and functional modules were implemented using Verilog hardware description language. After the syntax and functionality of the designed ASIC were rigorously verified using a field-programmable gate array development board, the designed ASIC was fabricated through the 0.18-μm complementary metal–oxide–semiconductor process of Taiwan Semiconductor Manufacturing Company. This ASIC caters to the specific requirements of three-phase induction motors. Measurement results indicated that the fabricated ASIC had a chip area of 0.974 × 0.976 mm2, a sampling frequency of 40 MHz, and power consumption of 0.5957 mW under a supply voltage of 1.8 V and an operating frequency of 10 MHz.

This study proposes a direct torque control (DTC) application-specific integrated circuit (ASIC) equipped with a neural network and a fuzzy hysteresis controller to achieve seamless control of a three-phase induction motor. In the proposed DTC system, feedback currents and voltages measured at the stator are fed into the hysteresis controller and a switching table. Subsequently, six-arm voltages are generated based on the voltage vector selector table to drive the RM5G inverter. However, severe switching noise is present in the power transistors of the inverter. These problems lead to numerous large ripples, instability, and delayed torque and flux responses at the stator. To address the aforementioned challenges, this study proposes a fuzzy controller to enhance flux signals. This controller incorporates a fuzzifier, a fuzzy rule base, and a defuzzifier. Additionally, a backpropagation neural network control is employed to improve torque signals. The multilayer neural network is utilized not only to calculate torque rapidly but also to enhance calculation accuracy. The proposed control method effectively reduces flux and torque errors, facilitating smooth control of the three-phase induction motor. After functional verification on an FPGA board, the proposed design is implemented on an ASIC fabricated using the TSMC$0.18-\mu \mathrm{m}$CMOS process. The results indicate a chip area of approximately$0.959\times 0.9584\text{mm}^{2}$and a power consumption of 2.2524 mW at a supply voltage of 1.8 V and an operating frequency of 10 MHz.

In this study, we propose a modified predictive direct torque control (PDTC) application-specific integrated circuit (ASIC), comprising a neural network (NN) proportional integral derivative (PID) controller, speed-sensorless control, fuzzy error controller, and seven-stage hysteresis controller, to alleviate the ripple problem induced by limited vector voltages and slow speed response in conventional direct torque control. Both flux and torque errors pass through the modified discrete multiple vector voltage switch table to obtain the required vector voltages, and the proposed NN PID controller is used to convert the speed error into a torque command. Notably, the motor speed is evaluated from the magnetic flux, which is calculated using two-phase currents and voltages. The speed-sensorless control not only accelerates the feedback control but also rotates more stably. The NN PID controller generates a torque command according to the speed error, which is obtained by subtracting the estimated predictive speed from the actual speed. The advantages of the proposed system are that it reduces the flux and torque ripples and increases the control stability by filtering out the external interferences. The Verilog hardware description language is used to implement the proposed PDTC ASIC system, and a field-programmable gate array development board is used to verify the designed functions.

This paper presents an Ethernet packet transformation and transmission architecture between Modbus transmission control protocol (Modbus/TCP) and universal serial bus (USB) 3.0 developed with a field-programmable gate array (FPGA) development board. The proposed architecture is used to complete packet transformation and transmission between Ethernet and USB 3.0 for application in plant automation. The Ethernet receiver receives and analyzes Modbus/TCP packets and sends the source address, destination address, IP header, and Modbus/TCP header to the register to verify the correctness of the packet. The Modbus/TCP packet is stored in static random access memory and awaits access by a USB 3.0 module. An FPGA development board (Intel DE10-Standard) is used for functional verification. The measured results show that the latency, throughput, and dynamic power are 18.845 ×s, 747.45 Mbps, and 142.17 mW, respectively, at a voltage of 1.8 V and operating frequency of 125 MHz.

This paper presents an intelligent packet transmission system between an Ethernet and a synchronous optical network involving format transformation based on a field-programmable gate array (FPGA) development board. Client data are fed to the RS485 port on the FPGA board (Tx) and then transformed into an Ethernet packet. The E/O converter (Tx) converts an electrical signal to an optical signal and transmits it through the optical fiber to the receiver. The O/E converter (Rx) converts an optical signal to an electrical signal, which is captured using the FPGA board. The signal is then sent to the client through the RS485 port. The client terminal can display the received data to verify the transceiver function. Optical fiber transmission has properties such as high speed, long distance, and low interference, whereas electrical transmission does not possess these features. The intelligent packet transformation and transmission mechanisms were implemented using the Verilog hardware description language and verified through the FPGA development board on the RS485 serial port. The measured results indicated that the operational frequency, data transfer rate of the RS485 port, power consumption, and chip size were 125 MHz, 115,200 bps, 137 mW, and 1.27 × 1.27 mm2, respectively, at a data volume of 8 bits and a first-in-first-out queue of 1K bytes.

This paper presents a modified direct torque control (MDTC) application-specific integrated circuit (ASIC), which includes a proportional-integral-derivative (PID) speed controller and five-stage fuzzy hysteresis, for reducing torque and flux ripples, which are induced by the low vector voltage and slow response speed of the traditional DTC circuit. The high-speed fuzzy PID controller and five-stage fuzzy hysteresis improve control stability. The proposed PID controller reduces the flux and torque ripples through the modified discrete multiple vector voltage (MDMVV). The proposed MDTC ASIC not only reduces torque and flux ripples but also enhances the stability of the control system. The proposed MDMVV generates four voltage vectors in a sampling cycle, whereas the conventional DTC generates a single voltage vector. Hardware description language was used to design and implement the motor control, and a programmable logic gate array board was used to verify the designed functions. The MDTC ASIC was fabricated using the 0.18-μm CMOS process with a chip area of 1.193 × 1.190 mm2. At an operating frequency of 10 MHz and a voltage of 1.8 V, the power consumption was determined to be 2.457 mW.

This paper presents a modified predictive direct torque control (PDTC) application specific integrated circuit (ASIC) with speed feedback controller in motor drive. The proposed PDTC ASIC not only decreases the ripple of hysteresis controller but also enhances the performance of motor controller. Verilog hardware description language (Verilog HDL) is used to implement the hardware architecture; and that an ASIC is fabricated in TSMC 0.18µm process with cell-based design method. Both switching and calculating delay times mainly contribute the ripples which degrade the control quality in motor drive. By using the predictive scheme, we not only improve the ripple issue of the traditional direct torque control technique, but also make the control system more stable by decreasing the time delay in hysteresis controller. According to the measured results, the proposed PDTC ASIC performs with the coverage of 99.10 % and the fault coverage of 98.28 % at the operating frequency of 50 MHz, the supplied voltage of 1.8 V and the power consumption of 218.7 mW.