3D integration with fine-pitch hybrid bonding offers a promising path to alleviate interconnect bottlenecks in conventional two-dimensional (2D) ICs, yet efficient 3D floorplanning remains challenging due to the enlarged solution space and non-uniform inter-die communication latency. Existing methods either extend 2D representations into 3D, leading to combinatorial complexity, or adopt partitioning-first pipelines that fix block-to-die assignments early and hinder joint optimization of floorplan, die assignment, and vertical connectivity. In this work, we present \textsc{Great3D}, a partitioning-free 3D floorplanning framework that directly optimizes a native 3D floorplan. \textsc{Great3D} formulates a unified objective that couples interconnect cost with a cycles-per-instruction (CPI)-derived latency term to capture the system-level impact of face-to-face (F2F) bonding. Algorithmically, it combines an SDP-based 3D global embedding with a dynamic-programming refinement for die assignment, followed by 2D continuous refinement with practical design constraints. \textcolor{blue}{Experiments on the GSRC and ATPlace benchmark suites show that \textsc{Great3D} consistently achieves strong wirelength and CPI quality against state-of-the-art 3D floorplanners. On GSRC, it reduces total wirelength by up to about $70\%$ (and by $2.40$--$2.74\times$ on average) over competing 3D-native floorplanners, and its dynamic-programming die-assignment stage further improves CPI by $9.5$--$17.8\%$, while maintaining competitive runtime on instances of up to a few hundred blocks.}

As a critical step in electronic design automation (EDA), global routing provides a guide to subsequent steps and provides valuable feedback to previous steps, including congestion, timing, and power estimation. However, given the complexity of timing and power calculation, it is difficult to estimate the impact on timing and power during the routing process. To address this issue, we propose a gradient-guided framework that computes the ''capacity sensitivity'' and ''resistance sensitivity'' of each segment to estimate their influence on the timing objectives. Integrating these two values as weights to constrain the changes in capacitance and resistance of the wire segments, we develop a timing-driven global router with superior performance. Power is also considered by optimizing the cells' switching power. Tested on ISPD25 Contest benchmarks, we can achieve 14.3% and 18.5% improvements in worst negative slack and total negative slack, respectively, with comparable congestion. With power optimization, we can further improve switching power by 10.6%.

3D ICs extend integration freedom beyond post-Moore limits and can improve performance. Yet, existing true-3D placers remain primarily wirelength-driven, and partition-based 3D flows struggle to incorporate timing during design-space exploration. Prior 2D timing-driven approaches often rely on RSMT-based routing lookahead, which is unstable under z-moves and lacks a smooth objective for gradient-based optimization; simple net weighting further fails to capture path-level timing. We present IDDA-3D, the first timing-driven placement framework for face-to-face (F2F) bonded 3D ICs. IDDA-3D introduces a quadratic RC formulation that models intra-/inter-die driver-sink delay as a differentiable timing cost for analytical placement. The RC parameters are derived directly from the technology library, ensuring that the model reflects physical delay accurately and remains applicable across diverse technology nodes without manual tuning. To handle the discrete nature of die assignment, we employ a finite-difference approximation (FDA)-based gradient computation with preconditioning, which integrates seamlessly with the analytical placement engine. Experimental results show that IDDA-3D improves total negative slack (TNS) by up to 44% and worst negative slack (WNS) by 22%, while maintaining competitive wirelength and runtime compared with state-of-the-art true-3D placers.

Accurate timing estimation during the routing stage is critical for modern VLSI design closure, especially under increasing crosstalk effects in advanced technology nodes. During the routing process, the crosstalk effect is usually modeled by predicting coupling capacitance with congestion information. However, such estimations are often overly pessimistic, as crosstalk-induced delay is influenced not only by coupling capacitance but also by the relative arrival times of signals. In this work, we propose ChronoTE, a novel edge-enhanced graph neural network (GNN) framework that performs crosstalk-aware net delay estimation by jointly modeling physical topology and timing characteristics. By embedding timing-window-aware features into edge representations, ChronoTE enables accurate delay prediction without requiring full routing or parasitic extraction. Experimental results on industrial-scale open-source designs demonstrate that ChronoTE, by delivering sign-off quality delay estimation in the early global routing stage, significantly accelerates design closure and contributes to area reduction.

As transistor size continues to scale down, process variation has become an essential factor determining semiconductor yield and economic return. The Liberty Variation Format (LVF) is the current industrial standard that expresses statistical timing behaviors based on single Gaussian model. However, it loses accuracy when the timing distribution is non-Gaussian due to growing process variations. This paper proposes a novel LVF2 distribution model that combines two weighted skewed-normal (SN) distributions, which better captures the multi-Gaussian timing distribution while maintaining backward compatibility with LVF. Experiments using TSMC 22nm standard cells show that, compared to LVF, LVF2 reduces binning error by 7.74X in delay and 9.56X in transition time, and reduces 3σ-yield error by 4.79X and 7.18X in delay and transition time, respectively. The error reduction for path delay is diminished due to Central Limit Theorem (CLT). But it is still 2X for a typical circuit path with 8 Fanout-of-4 (FO4) inverter delays.

Pre-routing timing estimation is vital but challenging since accurate net information is available only after routing and parasitic extraction. Existing methodologies predict the timing metrics with the help of the placement information of standard cells. However, neglecting the analysis of process variation effects hinders the precision of those methodologies, especially in sub-16nm technologies as delay distributions become asymmetric. Therefore, a deep-learning-based statistical timing prediction method is proposed to model process variation effects in the pre-routing stage. Congestion features and pin-to-pin features are fed into graph neural networks for post-routing interconnect parasitic and arc delay prediction. Moreover, a calibration method is proposed to compensate for the precision loss of the delay propagation. We evaluate our methods using open-source designs and EDA tools, which demonstrate improved accuracy in pre-routing timing prediction methods and a remarkable speed-up compared to traditional routing and timing analysis process.

In the advanced technology, the accuracy of cell and wire delay modeling are the key metrics for timing analysis. However, when the supply voltage decreases to the near-threshold regime, the complicated process variation effect causes the cell delay and the wire delay hard to model. Most researchers study cell or wire delay separately, ignoring the coefficients between them. In this paper, we propose an N-sigma delay model by characterizing different sigma levels$\mathbf{(-3\sigma {to}+3\sigma)}$of the cell and wire delay distribution. The N-sigma cell delay model is represented by the first four moments and calibrated by the operating conditions (input slew, output load). Meanwhile, based on the Elmore model, the wire delay variability is calculated by considering the effect of drive and load cells. The delay models are verified through the ISCAS85 benchmarks and the functional units of PULPino processor with TSMC 28 nm technology. Compared to the SPICE results, the average errors for estimating the$+/-\mathbf{3\sigma}$cell delay are 2.1 % and 2.7% and those of the wire delay are 2.4% and 1.6%, respectively. The errors of path delay analysis keep below 6.6% and the speed is 103X over SPICE MC simulations.

The advent of autonomous power-limited systems poses a new challenge for early design space exploration. The existing architecture-level power evaluation tools lose accuracy due to ignoring features of circuit-level behaviors and influences of process, voltage, and temperature variations. Although power estimations based on SPICE or PrimeTime PX (PTPX) are accurate enough, they come at the cost of long simulation time and are available only in very late phases of design flow. In this article, a fast and accurate dynamic power evaluation method is proposed, which estimates activity factors at the circuit level. The impact of process variation at the gate level is considered through the proposed effective capacitance model. Activity factors are then estimated by the model and input vectors of the circuit. Input vectors are generated by architecture-level simulations in the form of streaming. For real-time and high-speed power evaluation, a data streaming framework is proposed for massive parallelism. The cross-layer estimation is verified based on the functional units of PULPino processor running SPEC CPU2006 benchmarks. Compared with the SPICE results using SMIC 28-nm PDK, our cycle-by-cycle dynamic power analysis shows an average error of 5.4%. Meanwhile, our approach realizes 65.2% faster than the traditional PTPX simulation and 48.8% faster compared with the state-of-art cross-level evaluation method.

Wide supply voltage scaling is critical to enable worthwhile dynamic adjustment of the processor efficiency against varying workloads. In this paper, a cross-layer power and timing evaluation method is proposed to estimate the processor energy efficiency using both circuit and architectural information in a wide voltage range. The process variations are considered through statistical static timing analysis while the voltage effect is modeled through secondary iterated fittings. The error for estimating processor energy efficiency decreases to 8.29% when the supply voltage is scaled from 1.1V to 0.6V, while traditional architectural evaluations behave more than 40% errors.