VLDB 2026 Research / reviewers in the wild / expert
Surinder Sood
dblp:127/7056
· DBLP profile ↗
3ranked-venue papers
3as first author
2since 2021 · last 2022
0000-0003-1809-4255ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 2 · 2 first-author · 2 since 2021Theory of computation · 2 · 2 first-author · 2 since 2021Systems, architecture and hardware · 1 · 1 first-author
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Robust hardware-software Co-simulation framework for design and validation of Hybrid SystemsabstractModel based design of embedded controllers is prevalent across different industries. The final step in model based design is synthesis of hardware (or software) controller and then testing the synthesized controller in closed-loop with the plant model - this is termed as co-simulation. Standard cosimulation approaches use asynchronous communication fabric. However, they are known to suffer from race conditions, jitter, etc, making real-time property validation difficult. Current approaches to co-simulation problems either require complex middle-ware or require synthesis of the controller and plant for synchronous execution. However, these approaches are unsuited for hybrid system control design and validation, as they require the plant model to execute at an arbitrarily small simulation step, while the synthesized controller executes at its own rate if any. The small simulation step slows down the simulation and such a setup does not guarantee level crossing detection. In this paper, we propose a novel Metric Interval Temporal Logic (MITL) based validation and Hardware in Loop (HIL) co-simulation framework, which synchronizes and integrates the controller synthesized in hardware and the plant executing in software. A discrete controller handles a level crossing generated by the plant, which evolves on variable step size. The traces generated from the closed-loop operation of the overall system are used to validate MITL properties. Finally, the controller hardware and the plant model are adjoined via a communication architecture, whose sample time is dependent upon the robustness estimates of the MITL properties, which is necessary to guarantee validation correctness. Surinder Sood, Avinash Malik, Partha S. Roop |
MEMOCODE | 1 |
| 2022 | A novel approach to Real-time contract based reasoning for Hybrid SystemsabstractWorst Case Execution Time (WCET) analysis of large and complex hybrid systems can be time consuming. Contract based design allows for compositional reasoning of complex systems. Contracts justify the behavior of a system by way of assumptions (which are to be satisfied by the system environment) and guarantees, which are to be met by the system. Contracts also play a major role in compositional reasoning, refinement and re-usability of the system components. In this paper, we present a formal framework to enforce real-time contracts using Hoare triples, for synchronous system design and verification. In that regard, we propose real-time Hoare rules which are based on the WCET of the system and its components. We verify the real-time behavior of the system by applying these rules. These rules not only justify the system behavior and the behavior of its components but their timing as well. We also show that these Hoare rules are sound. Then we show that the synchronous composition of component level Hoare rules based contracts justify a system level contract. This real-time contract composition and reasoning technique which is based on real-time Hoare logic rules is the first ever attempt in synchronous system design and verification. Surinder Sood, Avinash Malik, Partha S. Roop |
MEMOCODE | 1 |
| 2020 | Robust Design and Validation of Cyber-physical SystemsabstractCo-simulation--based validation of hardware controllers adjoined with plant models, with continuous dynamics, is an important step in model-based design of controllers for Cyber-physical Systems (CPS). Co-simulation suffers from many problems, such as timing delays, skew, race conditions, and so on, making it unsuitable for checking timing properties of CPS. In our approach to validation of controllers, synthesised from their models, the synthesised controller is adjoined with a synthesised hardware plant unit. The synthesised plant and controller are then executed synchronously and Metric Interval Temporal Logic (MITL) properties are validated on the closed-loop system. The clock period is chosen, using robustness estimates, such that all timing properties that hold on the controller guiding the discretised plant model also hold on the original case of the continuous-time plant model guided by the controller. Benchmark results show that real-time MITL properties that are vacuously satisfied or violated due to co-simulation artefacts hold correctly in the proposed closed-loop validation framework. Surinder Sood, Avinash Malik, Partha S. Roop |
ACM Trans. Embed. Comput. Syst. | 1 |