This paper presents the design and implementation of a low-power fractional-N Phase-Locked Loop (PLL)-based frequency synthesizer fabricated in 130 nm BiCMOS technology for 60 GHz datalink applications. Driven by the semiconductor industry’s trend toward miniaturization, especially for implantable health monitoring systems, the PLL utilizes a push-push Colpitts voltage-controlled oscillator (VCO) that employs its second harmonic to achieve a 60 GHz output. The architecture integrates static and multi-modulus frequency dividers, a sigma-delta modulator, a phase/frequency detector, a charge pump, a loop filter, a built-in bandgap voltage reference (BGR), and a low-drop-out (LDO) regulator for optimal performance. Measurement results indicate the synthesizer operates within a frequency range of 59.3 GHz to 65 GHz while consuming only 140 mW from a single 1.5V DC supply. The PLL exhibits phase noise levels ranging from -88 dBc/Hz to -96 dBc/Hz at a 1 MHz offset across its frequency range. The proposed PLL design exhibits robust frequency stability and high integration capabilities, making it a viable solution for advanced biomedical sensors in health monitoring applications.

We present a highly-integrated transceiver system-on-chip (SoC) intended for Ku-band backhaul applications in the 12-14GHz frequency range. The chip is realized using Infineon’s 0.13μm SiGe BiCMOS technology and encapsulated in a wafer-level eWLB package. The many blocks comprising the circuit achieve competitive performance in measurement, such as an integrated VCO with a phase noise below -110dBc/Hz at a 1MHz offset, a receiver gain of 19dB and a transmitter with an output power of up to 16dBm. The chip also integrates a VGA and I/Q modulators in the TX chain, frequency dividers, LO multiplexers for an external LO feed, LO leakage cancellation circuitry and an SPI interface. The chip operates from a single 3.3V power supply, consuming 1.49W in transmit mode and 0.67W in receive mode, with the capability to support spectrally-efficient modulation schemes up to 64-QAM and data-rates up to 1.2Gb/s with the 16-QAM modulation.

This paper presents a 1 GHz low power Direct Digital Synthesizer (DDS) with sub-Hertz frequency resolution operating at 9.4 K. The proposed circuit is used as a signal generator for microwave (MW) driven qubit entanglement operations in trapped-ion quantum computers for improved gate fidelity. This is realized by utilizing the generated waveform as the carrier for the qubit’s driving signal. This signal is further frequency multiplied and envelope modulated to get the final qubit driving signal. The proposed mixed-signal-circuit operates at a 2.5 V/1.5 V analog and 1.5 V digital supply, 1 GHz input clock and consumes a total power of 27.64 mW. The frequency normalized-total power consumption, is only 27.64 µW/MHz. The DDS gives a worst case narrow band SFDR of 32.72 dB across the octave of frequencies to be synthesized. The design is manufactured in a 0.13 µm SiGe BiCMOS technology and has a core area of 0.69 mm2.

This paper presents an overview of the latest research results on integrated, cryogenic-compatible electronics for ion shuttling operation in Trapped-Ion Quantum Computers (TIQCs). Integrated circuit (IC) realization is essential to enable system scaling towards a larger number of qubits. Firstly, we review the specific challenges related to the shuttling operation and ion confinement. Consequently, implications on circuit design of an integrated shuttling controller system on chip (SoC) are discussed. Particularly, among other circuit design parameters, we analyze in detail the requirements on power and area consumption, noise performance, and cryogenic-compatibility. Secondly, we provide an overview on reported discrete solutions, eventually highlighting the need for a dedicated integrated shuttling controller SoC. Hence, state of the art integrated shuttling controller approaches are presented and reviewed. Finally, we conclude the paper with an outlook on promising integrated circuit concepts for shuttling controllers.

This paper presents a systematic comparison of two high-efficiency and high-gain D-band power amplifiers (PAs) realized in a 22 nm FDSOI CMOS technology. To enhance gain and differential-mode stability, both amplifiers are capacitively neutralized. The two PA test chips are realized each using a different physical implementation of the neutralization capacitance: a) MOM and b) MOS. Using these chips we analyze systematically in measurement the effects of different capacitor types on the circuit performance. We present PA measurements operating up to temperatures of 125 °C and under voltage variations. The PAs feature a high gain of 13 dB and 13.9 dB, while achieving a maximum saturated output power of 7.3 dBm and 6.6 dBm, respectively. Despite the high gain, the PAs offer a 3-dB bandwidth of at least 32 GHz and 27 GHz. Due to their low DC power consumption of only around 29 mW at an operating voltage of 0.8 V, the maximum power-added-efficiency (PAEmax) reaches high values of 12.2 % and 10.2 %, respectively.

The realization of autonomous, wearable, and implantable system-on-chip (SoC) for health monitoring applications poses several challenges, such as achieving ultralow size, cost, and power consumption, yet offering sufficient flexibility to reprogram and adapt the autonomously operating SoC during the course of treatment. Commonly, programmability is not considered for ultralow-power (ULP) biomedical SoCs, since a dedicated finite state machine (FSM) fixes the operation sequence, and instruction memory presents significant contributions to silicon area and power consumption. Based on a previously published tiny, programmable microarchitecture, this work proposes the strongly enhancedNanoController v2, for potential use in ultralow-power biomedical SoCs, and integrates it as a prototype chip in a 22-nm FDSOI-CMOS technology. By implementing a novel microcoded control unit and an automated design space exploration framework, which are made available open-source, the instruction set can be freely redefined to exploit application-specific properties. The benefits are increased code compaction, performance gain, and, consequently, decreased power consumption. In an extensive measurement campaign, a glucose sensor control application achieves 13.1% higher performance and 15.6% less code size in the best case, resulting in an extremely low power consumption of 660 nW (9% less than the reference),only by a different instruction setwithout hardware changes. Compared with other state-of-the-art small programmable microcontrollers, between 38% and 82% smaller code size and between 33% and 77% smaller silicon area and averaged power consumption could be shown. Based on the prototype results, a fully integrated glucose sensor chip will be evaluated in currently ongoing work.

This work presents an ultra-low-power, single-ended successive approximation register (SAR) analog-to-digital converter (ADC) designed explicitly to digitize sensor data. Due to the single-ended nature of the sensor’s output data, very efficient designs for differential SAR ADCs cannot be utilized. Hence, a monotonic capacitor switching procedure for single-ended inputs has been developed and is introduced in this paper. Re-charging of capacitances during the SAR algorithm is no longer required, resulting in significant energy savings compared to conventional approaches.The SAR ADC is implemented in a 22nm CMOS FDSOI technology. It achieves a measured signal-to-noise and distortion ratio (SNDR) of 49.1dB and a spurious-free-dynamic-range (SFDR) of 61dB. It draws a simulated 1.2μW yielding a Walden figure of merit (FoMW) of 50.2fJ/conversion step at a sampling rate of 100kS/s. The circuit occupies an area excluding pads of only 275 x 220μm2.

Abstract One of the key design requirements for any portable/mobile device is low power. To enable such a low powered device, we propose an embedded gesture detection system that uses spiking neural networks (SNNs) applied directly to raw ADC data of a 60GHz frequency modulated continuous wave radar. SNNs can facilitate low power systems because they are sparse in time and space and are event-driven. The proposed system, as opposed to earlier state-of-the-art methods, relies solely on the target’s raw ADC data, thus avoiding the overhead of performing slow-time and fast-time Fourier transforms (FFTs) processing. The proposed architecture mimics the discrete Fourier transformation within the SNN itself avoiding the need for FFT accelerators and makes the FFT processing tailored to the specific application, in this case gesture sensing. The experimental results demonstrate that the proposed system is capable of classifying 8 different gestures with an accuracy of 98.7%. This result is comparable to the conventional approaches, yet it offers lower complexity, lower power consumption and faster computations comparable to the conventional approaches.

Contactless detection of hand gestures with radar has gained a lot of attention as an intuitive form of human-computer interface. In this paper, we propose an air-writing system, writing of linguistic characters or words in free space by hand gesture movements using a network of milli-meter wave radars. Most of the works reported in the literature are based on deep learning approaches, which in some cases can involve prohibitively large computational/energy costs making them undesirable for edge IoT devices, where energy efficiency is the prime concern. We propose a highly energy-efficient air-writing system using spiking neural networks, where the trajectory of the character created by fine range estimates together with trilateration from a network of radars are recognized and classified by a spiking neural network (SNN). The proposed system achieves a similar level of classification accuracy (98.6%) compared to the state-of-the-art deep learning methods for 15 characters containing 10 alphabets (A to J) and 5 numerals (1 to 5). Additionally, the proposed SNN model is of 3.7 MB in size making it memory efficient in terms of storage. We demonstrated the proposed method in real-time using a network of 60-GHz frequency-modulated continuous wave radar chipset.

Health monitoring devices are gaining popularity both as wellness tools and as a source of information for healthcare decisions. In this work, we use Spiking Neural Networks (SNNs) for time-series forecasting due to their proven energy-saving capabilities. Thanks to their design that closely mimics the natural nervous system, SNNs are energy-efficient in contrast to classic Artificial Neural Networks (ANNs). We design and implement an energy-efficient privacy-preserving forecasting system on real-world health data streams using SNNs and compare it to a state-of-the-art system with Long short-term memory (LSTM) based prediction model. Our evaluation shows that SNNs tradeoff accuracy (2.2× greater error), to grant a smaller model (19% fewer parameters and 77% less memory consumption) and a 43% less training time. Our model is estimated to consume 3.36μJ energy, which is significantly less than the traditional ANNs. Finally, we apply ε-differential privacy for enhanced privacy guarantees on our federated learning-based models. With differential privacy of ε = 0.1, our experiments report an increase in the measured average error (RMSE) of only 25%.

Spiking Neural Networks represent the third generation of biologically inspired systems for signal processing. They are associated with a particularly efficient and thus low-energy possibility of computing. However, this advantage can only be fully achieved if these networks utilize special neuromorphic circuits. In this work, an analog Spiking Neural Network Phase Detector is presented, from conceptual formulation to implementation in a${130}~{\text {nm}}$BiCMOS process. The phase detector is capable of directly processing various continuous-time signals up to a frequency of${200}~{\text {MHz}}$, while consuming just${840}~{\mu \text {W}}$. The phase difference between the signal under test and the reference signal that shall be detected is adaptable. Experimental findings confirm the simulative investigations. The proposed method presented in the paper provides an entry-level approach to designing more complex analog spiking neural networks.

Hand gesture recognition has become an increasingly important functionality in intelligent human-computer interfaces, finding applications in automotive, gaming and consumer industries. In this paper, we present an embedded gesture recognition system using frequency modulated continuous wave radar operating at 60 GHz. To facilitate low-power and low latency operation of the proposed system, spiking neural networks are used which are sparse in time and space, and event-driven. The experimental results demonstrate that the proposed neuromorphic implementation is capable of achieving a high recognition rate of 97.5% which is comparable to its deep learning counterparts in identifying radar gestures, namely up-down, down-up, swipe and finger rub.

Air-writing systems offer users a virtual board to write characters or words in free space using fingers or hand movements. Several works have been proposed in literature that aim to use different sensors to enable such a system as an alternative to the keyboard and click form of human-machine interfaces. The advancement of miniature radar sensors and deep learning has enabled precise estimation and tracking of finger or marker movement followed by character recognition to offer an effective air-writing solution. However, deviating from earlier works in literature that make use of a network of radars to effectively track and recognize characters, in this paper, we propose to use only one or two radars to sense the local hand trajectory. We propose to use 1D temporal convolutional network (TCN) for simultaneous feature extraction and temporal modeling to recognize the drawn character from the local target trajectory. A dataset with 3750 character instances has been recorded using a 60-GHz millimeter-wave frequency-modulated continuous wave radar (FMCW) radar. We demonstrate the proposed end to end solution achieves a mean accuracy of 99.11% and 91.33% for two radar and one radar-based solution respectively outperforming other deep architectures.

Hand gesture and motion sensing offer an intuitive and natural form of human-machine interface. Air-writing systems allow users to draw alpha-numerical or linguistic characters in the virtual board in air through hand gestures. Traditionally, radar-based air-writing systems have been based on a network of radars, at least three, to localize the hand target through trilateration algorithm followed by tracking to extract the drawn trajectory, which is then followed by recognition of the drawn character by either Long-Short Term Memory (LSTM) utilizing the sensed trajectory or Deep Convolutional Neural Network (DCNN) utilizing a reconstructed 2D image from the trajectory. However, the practical deployments of such systems are limited since the detection of the finger or hand target by all three radars cannot be guaranteed leading to failure of the trilateration algorithm. Further placement of three or more radars for the air-writing solution is neither always physically plausible nor cost-effective. Furthermore, these solutions do not exploit the full potentials of deep neural networks, which are generally capable of learning features implicitly. In this paper, we propose an air-writing system based on a network of sparse radars, i.e. strictly less than three, using 1D DCNN-LSTM-1D transposed DCNN architecture to reconstruct and classify the drawn character utilizing only the range information from each radar. The paper employs real data using one and two 60 GHz milli-meter wave radar sensors to demonstrate the success of the proposed air-writing solution.