Timing closure, which is to meet the design's timing constraints, is a key problem in the physical design flow. During the timing optimization process, buffers can be used to speedup the circuit or serve as delay elements. In this paper, we study the hold-violation removal problem for today's industrial designs. Discrete buffers, accurate timing models/analysis, and complex timing constraints make the problem difficult and time-consuming to solve. In this paper, we first present a linear programming-based methodology to model the setup and hold-time constraints. Then based on the solution to the linear programming, buffers are inserted as delay elements to solve hold violations. In the experiment, our approach is tested on industrial designs, then runs with the industrial optimization flow, and better results in terms of hold violations and runtime are reported.

Over the last decade, transistor dimensions have shrunk rapidly by a factor of ten, while chip sizes have increased many folds and so have the scenarios in which they are expected to function. Silo technology development of yester years has all but disappeared as clear boundaries between various stages of the flow evaporate--need for resynthesis can be felt as late as post routing and necessity for understanding signal integrity and manufacturing as early as pre-placement. This leads designers to explore newer techniques to meet their power and performance targets and EDA vendors to retool and reinvent algorithms for sub teen nanometer technologies.