An energy harvester based on the electromagnetic induction effect exploiting the pitch oscillation of a sensor buoy is presented. An experimental prototype has been tested to extract the main parameters of the system.

This demo presents an innovative wireless sensor platform for oxygen monitoring, featuring LoRa connectivity and a unique battery-free operation to ensure maintenance-free usage. The platform integrates an advanced oxygen sensor and leverages LoRa technology to transmit data efficiently over long distances. Powered by a photovoltaic cell, the system is independent of conventional batteries, eliminating the need for periodic replacements. The photovoltaic cell supplies energy for the sensor’s operation and charges a 1F supercapacitor, ensuring continuous operation without light. The 1F supercapacitor allows the system to acquire data from the oxygen sensor and transmit it via LoRa connectivity with a configured spreading factor of 7 every 10 minutes for up to 10 hours without light.

A fully synthesizable rail-to-rail dynamic voltage comparator referring to different technology nodes and supply voltages down to 0.3V is presented in this paper. The analyzed circuit is composed of standard cells only so that the design flow can be automated, and based on its digital nature, it enables a supply voltage scaling down to deep sub-threshold. The specifications of the same topology are investigated with post-layout simulations under different technology nodes such as 180nm, 130nm, and 40nm and across scaled supply voltage ranging from 0.9 down to 0.3 V. Delay versus common and differential mode of the input and power and offset versus common mode. On this basis, pros and contras across technology and voltage scaling are highlighted to suit integration into sensor nodes for the Internet of Things and related applications.

This paper presents an ultra-low-power, low-voltage universal multi-mode Gm-C filter, designed in CMOS technology. The proposed filter uses only three transconductance operational amplifiers (OTAs) operating in a sub-threshold region: this leads to a significant reduction in energy consumption compared to previous solutions reported in the literature. Furthermore, the proposed filter can operate in four different functional modes, namely voltage, current, transconductance, and trans-resistance, without requiring extra active elements. Finally, the proposed filter for the band-pass responses features a power consumption of 32nW with a voltage supply of 0.5V, with a center frequency of 462Hz which can be considered for biomedical applications.

This paper presents and compares two single-ended inverter-based amplifier topologies, with and without active frequency compensation, both with the same area and the same biasing circuits. Thanks to adaptive voltage scaling and body biasing, the proposed circuits show robustness to the effect of the process, voltage, and temperature (PVT) variations. In particular, post-layout simulations referring to 180 nm technology process show a supply voltage insensitivity in the range from 6 V down to 2.5 V. The possibility of being robust to uncertain and unreliable supply voltage changes suppresses the need for an additional voltage reference and makes the proposed circuits well-suited for energy-harvesting systems-on-chip.

In this paper, a low-design effort, compact analog-to-digital converter (ADC) based on pulse-width modulation with a high level of digital (highly synthesizable) building block is described. Thus, the topology can take advantage of exploiting digital design tools offering supply-voltage scalability although relying on minimum re-design of the core block. The operating principle is based on the charge and discharge of a timing capacitor that allows an input-voltage-to-duty-cycle conversion. The duty cycle, in turn, enables the count of a counter exited by a ring oscillator. Post-layout time-domain simulations of the ADC performed at 180nm show a power consumption of 494 nW with a sample rate of 5 kS/s, 5.6 ENOB at 0.4 V supply voltage, and a compact area of 7200 μm2. The very low power consumption makes the proposed circuits very well suited for energy-harvested systems-on-chip for Internet of Things applications.

In this work, a capacitance-to-digital converter (CDC) suitable for direct energy harvesting is introduced. The nW peak power and the ability to operate at any supply voltage in the 0.3-1.8 V range allow complete suppression of any intermediate DC-DC conversion, and hence direct supply provision from the harvester, as demonstrated with a mm-scale solar cell. The proposed CDC architecture eliminates the need for any additional support circuitry, preserving true nW-power operation, and reducing design and integration effort. In detail, the architecture is based on a pair of double-swappable oscillators, and avoids the need for any voltage/current/frequency reference circuit in the oscillator mismatch compensation. The digital and differential nature of the architecture counteracts the effect of process/voltage/temperature variations. A load-agnostic one-time self-calibration scheme compensates mismatch, and can be run from boot to run stage of the chip lifecycle. The proposed self-calibration scheme suppresses any trimming or testing time for low-cost systems, and avoids any input capacitance disconnection requirement. A 180-nm testchip shows 7-bit ENOB down to 0.3 V and 1.37-nW total power, when powered by a 1-mm2 indoor solar cell down to 10 lux (i.e., late twilight).

In this paper, passive-less fully-digital operational transconductance amplifiers (DIGOTA) for energy- and area-constrained systems are modeled and analyzed from a design viewpoint. The digital behavior of DIGOTAs is modeled as an equivalent small-signal differential-mode circuit with zero bias current, and a common-mode feedback loop operating as a self-oscillating threshold sampler. Such continuous-time equivalent circuits are used to derive an explicit model of the main performance parameters that are generally adopted to characterize OTAs. This provides an insight into circuit operation and allows to derive practical guidelines to achieve a given design target. Among the others, an explicit model is derived for the DC gain, the frequency response, the gain-bandwidth product, the input-referred noise, and the input offset voltage. The models are validated via direct comparison with multi-die measurement results in CMOS 180 nm. From an application viewpoint, the voltage (power) reduction down to 0.25 V (sub-nW) uniquely enable direct harvesting (e.g., with solar cells), suppressing any intermediate DC-DC conversion stage. This further enhances the area efficiency advantage of DIGOTA stemming from its fully-digital nature, making it well suited for cost-sensitive and purely-harvested systems.

In this paper, two circuit topologies of pW-power Hz-range wake-up oscillators for sensor node applications are presented. The proposed circuits are based on standard cells utilizing the Dynamic Leakage Suppression logic style [4]-[5]. The proposed oscillators exhibit low supply voltage sensitivity over a wide supply voltage range, from nominal voltage down to the deep sub-threshold region (i.e., 0.3 V). This enables direct powering from energy harvesters or batteries through their whole discharge cycle, suppressing the need for voltage regulation. Post-layout time-domain simulations of the proposed oscillators in 180nm show a power consumption of 1.4-1.7pW, a supply-sensitivity of 55-40%/V over the 0.3V-1.8V supply voltage range, and a compact area down to 1,500μm2. The very low power consumption makes the proposed circuits very well suited for energy-harvested systems-on-chip for Internet of Things applications.

A novel rail-to-rail dynamic voltage comparator is presented in this paper. The proposed circuit is fully synthesizable, as it can be designed with automated digital design flows and standard cells, and can operate at very low voltages down to deep sub-threshold. Post-layout simulations show correct operation for rail-to-rail common-mode inputs at a supply voltageVDDdown to 0.3 V. At such voltage, the input offset voltage standard deviation is less than 28 mV (8 mV) over the rail-to-rail common-mode input range (aroundVDD/2). The digital nature of the comparator and its ability to operate down to deep sub-threshold voltages allow its full integration with standard-cell digital circuits in terms of both design and voltage domain. The ease of design, the low area and the voltage scalability make the proposed comparator very well suited for sensor nodes, integrated circuits for the Internet of Things and related applications.