Reversible logic synthesis is a crucial component in quantum electronic design automation. While rule-based methodologies have gained prominence in reversible circuit optimization, the completeness of the transformation rule systems is a longstanding problem in this domain. In this work, we propose the first complete set of transformation rules for reversible circuits, comprising five fundamental rules: any two equivalent reversible circuits can be transformed into each other using the rules. To prove the completeness, a canonical circuit representation for reversible functions is introduced, and we show that every reversible function is computed by a unique reversible circuit in the canonical form, and any reversible circuit can be transformed into its canonical form by applying the rules.

Abstract This paper presents the logics with second-order quantifiers that range over relations of polylogarithmic size (log-quantifiers). The logic $\text{SO}^{\text{plog}} \text{-} \text{FO}$ is constituted of the formulas that extend first-order formulas by log-quantifier prefixes. We show that $\text{SO}^{\text{plog}} \text{-} \text{FO}$ collapses to its binary fragment where log-quantifiers range only over unary and binary relations. We further investigate the 0-1 law for $\text{SO}^{\text{plog}}\text{-}\text{FO}$, demonstrating that it fails in general, yet holds for its monadic existential fragment over the vocabulary that contains only unary relation symbols. Finally, we study the logical characterizations for complexity classes with limited non-determinism. On ordered structures, we show that if a logic $\mathcal L$ captures a complexity class $\mathcal C$, then the logic $\varSigma ^{\log ^{k}}_{1}\text{-}\mathcal L$ captures the complexity class $GC(\log ^{k+1}(n), \mathcal C)$, where $\mathcal L \in \{\text{DTC}, \text{TC}, \text{IFP}\}$. Consequently, $\varSigma _{1}^{\text{plog}}\text{-} \text{IFP}$ captures $\beta \text{P}$ on ordered structures.

We study the expressive power and complexity of second-order revised Krom logic (SO-KROM$^{r}$). On ordered finite structures, we show that its existential fragment $\Sigma^1_1$-KROM$^r$ equals $\Sigma^1_1$-KROM, and captures NL. On all finite structures, for $k\geq 1$, we show that $\Sigma^1_{k}$ equals $\Sigma^1_{k+1}$-KROM$^r$ if $k$ is even, and $\Pi^1_{k}$ equals $\Pi^1_{k+1}$-KROM$^r$ if $k$ is odd. The result gives an alternative logic to capture the polynomial hierarchy. We also introduce an extended version of second-order Krom logic (SO-EKROM). On ordered finite structures, we prove that SO-EKROM collapses to $\Pi^{1}_{2}$-EKROM and equals $\Pi^1_1$. Both SO-EKROM and $\Pi^{1}_{2}$-EKROM capture co-NP on ordered finite structures.

Quantum circuit mapping is an essential process required by executing quantum circuits using a noisy intermediate-scale quantum (NISQ) device. Since qubits and quantum gates of a NISQ device are error-prone and variable in quality, it is crucial to choose qubits or quantum gates in a variation-aware manner to maximize the success rate of executing circuits. To this end, this article proposes a variation-aware method for quantum circuit mapping through the cooperation of multiple agents. Each agent in the proposed method can gradually construct a physical circuit that respects the device's connectivity constraints by inserting a SWAP gate at each step. Moreover, at each step, the circuit information of each agent is shared within the agent population through a communication mechanism that combines global and local information exchange, so that agents with poor fitness can get an opportunity to improve their physical circuits. The experimental results on extensive benchmark circuits confirm that the proposed method can effectively and consistently improve the overall circuit fidelity compared with the state-of-the-art methods.

The qubit mapping approach serves to transform a quantum logical circuit (LC) into a physical one that satisfies the connectivity constraints imposed by the noisy intermediate-scale quantum (NISQ) devices. The quality of the physical circuit generated by a mapping approach depends largely on the initial mapping, which specifies the correspondence between the qubits in the LC and the qubits on the NISQ device. There are a total of$n!$different initial mappings for a qubit mapping problem with$n$qubits, and among them, there is at least one initial mapping corresponding to the smallest physical circuit that this mapping approach can output. Finding such an initial mapping is very important for reliable computations on the NISQ device. To this end, we propose an iterated local search framework as well as a heuristic circuit mapper. In this framework, we perform multiple local searches on the space of initial mappings, and during each local search, several promising neighborhoods of the current initial mapping are generated and evaluated by invoking the circuit mapper in a forward or a backward manner. This framework provides a way for the qubit mapping approach to find the best physical circuit that it can produce, allowing it to trade time for circuit quality, which is necessary in the NISQ era. The experimental results demonstrate the stability, scalability, and effectiveness of this approach in reducing the number of additional gates. Moreover, although this approach is a multipass circuit mapping process, it can generate a good-quality physical circuit within half an hour, even for the circuit with more than 10 000 gates.

Metric Temporal Logic (MTL) and Timed Propositional Temporal Logic (TPTL) are quantitative extensions of Linear Temporal Logic (LTL) that are prominent and widely used in the verification of real-timed systems. We study MTL and TPTL as specification languages for one-counter machines. It is known that model checking one-counter machines against formulas of Freeze LTL (FLTL), a strict fragment of TPTL, is undecidable. We prove that in our setting, MTL is strictly less expressive than TPTL, and incomparable in expressiveness to FLTL, so undecidability for MTL is not implied by the result for FLTL. We show, however, that the model-checking problem for MTL is undecidable. We further prove that the satisfiability problem for the unary fragments of TPTL and MTL are undecidable; for TPTL, this even holds for the fragment in which only one register and the finally modality is used. This is opposed to a known decidability result for the satisfiability problem for the same fragment of FLTL.

Metric temporal logic (MTL) and timed propositional temporal logic (TPTL) are quantitative extensions of linear temporal logic, which are prominent and widely used in the verification of real-timed systems. It was recently shown that the path checking problem for MTL, when evaluated over finite timed words, is in the parallel complexity class NC. In this paper, we derive precise complexity results for the path-checking problem for MTL and TPTL when evaluated over infinite data words over the non-negative integers. Such words may be seen as the behaviours of one-counter machines. For this setting, we give a complete analysis of the complexity of the path-checking problem depending on the number of register variables and the encoding of constraint numbers (unary or binary). As the two main results, we prove that the path-checking problem for MTL is P-complete, whereas the path-checking problem for TPTL is PSPACE-complete. The results yield the precise complexity of model checking deterministic one-counter machines against formulae of MTL and TPTL.