Summary Soft errors in network‐on‐chip (NoC) such as single bit upsets and multibit upsets cause hazardous effects such as congestion, deadlock, livelock, and corruption of data. Error‐correcting codes (ECCs) are the best choices to handle these soft errors in links and memory buffers of NoC, which is the need of all modern systems, including internet of thing (IoT) edge devices. Many of these ECCs cannot correct both random and burst errors. Specific codes possess the correction and detection capability at the cost of an increase in area, latency, and energy. In this article, a coding technique is proposed by using a single error correction double error detection‐triple adjacent error correction‐six adjacent error detection (SEC‐DED‐TAEC‐6AED) (24,16) I5, that provides both random and burst error fault tolerance for NoC. The proposed technique decreases the area, energy, and latency cost of the whole NoC. It also reduces the area overhead to 173.41% and 117.91% compare to joint crosstalk avoidance multiple error correction (JCAMEC) and joint crosstalk multiple error correction (JMEC), respectively. Besides, the delay overhead of the proposed technique reduces to 4.2% and 91.97% compared with JCAMEC and JMEC, respectively. The simulation results show that the proposed code possesses an enhanced ability of error correction and detection with 3.5 times less redundant bits and a 30% fast code rate compared with JMEC and JCAMEC. Hence, the proposed scheme can effectively be used for detecting and correcting single and multiple bit errors for on‐chip communication.