As the manufacturing technology keeps scaling, crosstalk noise induces a greater impact on timing. Although many previous works proposed techniques like timing correlation, functional correlation and path refinement to consider crosstalk noise during static timing analysis, they often suffered from descendant problems including overly-pessimistic timing bound, bad aggressor selection and false paths. Therefore, in this paper, a coupling-aware functional timing analysis tool named CA-FTA is proposed to tame the three problems stated above and to derive a tighter timing bound for the true longest path. Experimental results show that CA-FTA averagely reduces timing bounds of those obtained from crosstalk STA (with path refinement) by 7.26% on several ISCAS'85 and ISPD-2012 benchmark circuits (in particular, by 34.6% for b19). As a result, CA-FTA successfully solves the aggressor-selection problem as well as the false-path problem and relaxes more margins when considering crosstalk noise.

In the nanometer era where the operating speed of a chip decides its price, design companies rely on high-qualty speed binning approaches to maxmizie their profits. The conventional speed binning approach is legacy (i.e. structural) since functional tests are too expensive to derive. Besides legacy and functional tests, recent studies tried to apply the notion of delay testing for deriving speed-binning patterns; however, all of them could not determine the number of patterns required for speed-binning nor taking process variation into consideration. Therefore, in this paper, we propose a speed-binning pattern generation (SBPG) method to deterministically generate a high-quality pattern set for speed binning. This SBPG mainly consists of two core techniques: (1) empirical variation sampling (EVS) and (2) functional timing analysis (FTA), which efficiently derives few high-quality patterns from a small number of learning samples. SBPG achieves a satisfactory accuracy (> 99% on average) for five benchmark circuits under various conditions of process variation, and is shown to be an efficient solution for speed binning.

Timing analysis becomes profound for modern VLSI designs. Functional timing analysis (FTA) has emerged to eliminate false paths and provide better timing closure than traditional static timing analysis (STA). However, signal transitions effect, such as multiple input switching (MIS), which changes the pin-to-pin delay of a gate as well as the overall circuit delay, has not yet been considered in FTA. Therefore, a Transition-Aware FTA (TA-FTA) engine using a novel four-valued encoding for calculating true delay under the signal-transition effect is developed in this work. However, timing analysis becomes sophisticated once the signal-transition effect is concerned. Therefore, two techniques, cone separation and filtering (CSF) and quadratic dynamic search (QDS), are also proposed to speed up TA-FTA by more than two orders in time. Experimental results shows that after considering the MIS effect, in the benchmark circuits, the delay reported by our TA-FTA increases by 23% on average and by 38% for the worst case.

Multi-core machines enable the possibility of parallel computing in Automatic Test Pattern Generation (ATPG). With sufficient computing power, previously proposed parallel ATPG has reached near linear speedup. However, test inflation in parallel ATPG yet arises as a critical problem and limits its practicality. Therefore, we developed a parallel ATPG system that incorporates (1) concurrent interruption (CI), (2) ripple compaction (RC) and (3) fan-in-cone based fault ordering (FIC) to deal with such problem. Concurrent interruption aborts test generation on simultaneously detected faults by fault simulation. Ripple compaction combines tests for different faults while fan-in-cone based fault ordering strategically arranges the fault list to reduce the number of test generations and thus speeds up the ATPG process. According to our experiments, the proposed parallel ATPG system effectively reduces 11% pattern count and achieves ~0% test inflation while maintaining an average of 6.5X speedup with no attenuation in fault coverage on experimental circuits.

General-purpose computing on graphics processing unit (GPGPU) enables the possibility of parallel computing for Static Timing Analysis (STA) of VLSI designs. However, memory access and synchronization between massively many cores become challenges to parallelizing STA. In this work, we developed a fast CUDA-Accelerated STA engine (named CASTA) that incorporates four novel techniques including Table-Index Remapping (TIR), Texture-Accelerated Rendering (TAR), Cell Levelization & Type Sorting (CLTS) and Timing-Table Restructuring(TTR) to enable high parallelism. Cell Levelization & Type Sorting (CLTS) levelizes cells and sort their types in order to efficiently access the same timing library. Timing-Table Restructuring (TTR) modifies the data structure for timing signals of cells to increase memory throughput. Table-Index Remapping (TIR) re-maps the axes of timing tables to retrieve data more efficiently while Texture-Accelerated Rendering (TAR) expands look-up tables (LUTs) to avoid extrapolation and stores LUTs in the texture for speed. As a result, our experimental result indicates that CASTA successfully enables high parallelism and outperforms a commercial tool by a three-order speedup on average over several benchmark circuits.

Power cost and wire cost are two most critical issues in scan-chain optimization for modern VLSI testing. Many previous works used layout-based partitioning and greedy heuristics to synthesize multiple scan chains, making themselves suffer from (1) cost-metric monotonicity and (2) crossing-edge problem. Therefore, in this paper, we propose cost-driven spectral ordering including (1) cost-driven k-way spectral partitioning and (2) greedy non-crossing 2-opt ordering to resolve two above problems, respectively. Experiments show that different cost metrics can be properly addressed in k-way spectral partitioning. Moreover, our cost-driven spectral ordering achieves averagely 9% mixed (power-and-wire) reduction than two previous works on benchmark circuits, which evidently demonstrates its effectiveness on multiple scan-chain synthesis.

This brief addresses the problem of scan-chain ordering under a limited number of through-silicon vias (TSVs), and proposes a fast two-stage algorithm to compute a final order of scan flip-flops. To enable 3-D optimization, a greedy algorithm, multiple fragment heuristic, is modified and combined with a dynamic closest-pair data structure, FastPair, to derive a good initial solution in stage one. Stage two initiates two local refinement techniques, 3-D planarization and 3-D relaxation, to reduce the wire (and/or power) cost and to relax the number of TSVs in use to meet TSV constraints, respectively. Experimental results show that the proposed algorithm results in comparable performance (in terms of wire cost only, power cost only, and both wire-and-power cost) to a genetic-algorithm method but runs two-order faster, which makes it practical for TSV-constrained scan-chain ordering for 3-D-IC designs.