In the physical design of integrated circuits, clock tree synthesis (CTS) plays a crucial role in terms of timing closure and overall design convergence. The existing clock tree (CT) optimization methods usually prefer to balance both clock edges, and the key insight of this article is that the clock work edge does not need to keep balance with another nonwork edge for the widely employed single-edge triggered circuits. This motivates us to achieve CT optimization by improving the performance of the work edge while sacrificing the performance of another edge. To this end, complementary asymmetrical uniform transistor sizing (CAUTS) methodology is proposed, which enables us to: 1) improve those conflicted metrics in systematic ways, including clock latency, power, and so on and 2) perform CTS optimization without any clock buffer insertion and clock routing adjustment and thus without area penalty. Experimental results based on the first-generation FinFET technology with six benchmark circuits and four industry intellectual properties (IPs) demonstrate that: 1) the clock latency is reduced by 5.9%–19.8% at each corner for all designs; 2) the clock power is reduced by 2.45%–15.12% at each corner for all designs; 3) setup timing is improved for all designs, and the total negative slack (TNS) of setup timing for unclean corners can be reduced by 10.9%–73.6%; and (4) hold timing is improved for all designs, and the TNS of hold timing can be reduced by 5.2%–19.8% for four industry IPs.