Measuring building setbacks and heights along streets is important for evaluating the variability of streetscape skeletons, the 3D spaces of streets defined by the arrangement of surrounding buildings. Its evaluation requires computing the streetscape width, defined as the front road width of a building plus the setbacks of both sides of the front roads, the building heights and the ratio of the streetscape width to the building height, known as the streetscape width-to-height ratio. However, measuring building setbacks and streetscape widths with geographical information systems (GIS) workstations remains theoretically and technically challenging because conventional methods fail to define the ambiguous boundaries of streetscape skeletons. To address this issue, we developed a new method for defining and measuring building setbacks and streetscape widths automatically and in a consistent way. A new basic spatial unit was also developed for evaluating the variability in building setbacks, heights, streetscape widths and streetscape width-to-height ratios not only in plots focusing on classical urban morphologies but also along streets focusing on a pedestrian perspective. The method contributes practically to the measurement and evaluation of streetscape skeletons in a bottom-up way at fine intervals without the need for setting predetermined spatial units. KEY POLICY HIGHLIGHTSMeasuring building setbacks and heights along roads is important for evaluating the variability of streetscape skeletons.However, measuring these in an actual complex urban space without vagueness on a GIS workstation is difficult.We have developed a new method for defining and measuring building setbacks and streetscape widths automatically.A new basic spatial unit for evaluating streetscape skeletons is proposed focusing on the plot geometry and a pedestrian perspective.The method contributes to the evaluation of streetscapes in a bottom-up way at fine intervals without setting predetermined spatial units.

The spatial patterns of the generation and accumulation of vacant plots tend to be randomly distributed. This phenomenon, which represents morphological changes in urban areas, is called urban perforation. Urban perforation should be considered when discussing the spatial compaction of existing morphological urban areas; therefore, the morphological changes in urban areas caused by urban perforation must be simulated. However, suitable simulation methods have not been developed. This study applied the thinning point process developed in stochastic geometry to simulate the generation and accumulation of vacant plots and answered the following research questions based on empirical analysis in Sakura, Japan: (1) Can the thinning point process be used to simulate spatially random patterns of vacant plot generation in each built cluster? (2) Will accumulated vacant plots exhibit spatially random patterns in each built cluster after repeating the thinning point process? Evaluations of simulation performance revealed that the thinning point process did not always produce spatially random patterns of vacant plot generation and accumulation; however, the simulated dispersed patterns were logically consistent with urban perforation and revealed fragmented vacant plots. The results of this study may be used to predict future morphological urban areas in an era of urban shrinkage.

In the COVID-19 pandemic, keeping a two-metre physical distance (called social distancing) from others is a critical action to limit the amount of social contact among individuals. Thus, regulating the number of persons in a space is one means to limit social contact and ensure physical distancing among people. In addition to the privacy concerns of individuals’ locations, the lack of elevation information can result in false positive cases for people who are horizontally close but vertically apart beyond the social distance. Therefore, we develop a normative model of the statistical distribution of physical distances to estimate the number of persons not social distancing in a three-dimensional complex built space from the current number of persons in the space (i.e. population density) present on an hourly basis. We conduct an empirical case study in the districts around the central stations of 13 of Japan’s prefectures. To determine the number of people not social distancing in these districts, the proposed model uses open data such as the number of persons before the national emergency declaration, the ratio of the number of persons after the declaration to that before, and the floor area ratio specified by land use regulations in these districts.

The aim of this article is to describe a convenient but robust method for defining neighbourhood relations among buildings based on ordinary Delaunay diagrams (ODDs) and area Delaunay diagrams (ADDs). ODDs and ADDs are defined as a set of edges connecting the generators of adjacent ordinary Voronoi cells (points representing centroids of building polygons) and a set of edges connecting two centroids of building polygons, which are the generators of adjacent area Voronoi cells, respectively. Although ADDs are more robust than ODDs, computation time of ODDs is shorter than that of ADDs (the order of their computation time complexity is O(nlogn)). If ODDs can approximate ADDs with a certain degree of accuracy, the former can be used as an alternative. Therefore, we computed the ratio of the number of ADD edges to that of ODD edges overlapping ADDs at building and regional scales. The results indicate that: (1) for approximately 60% of all buildings, ODDs can exactly overlap ADDs with extra ODD edges; (2) at a regional scale, ODDs can overlap approximately 90% of ADDs with 10% extra ODD edges; and (3) focusing on judging errors, although ADDs are more accurate than ODDs, the difference is only approximately 1%.

The size distribution of urban blocks is important for the characterisation of urban block patterns and is known to follow several parametric statistical distributions. However, it has not previously been analysed on the basis of a normative plane tessellation and in terms of urban block density and mean road width. In this article, we formulate the size distribution of Voronoi cells using the gamma distribution estimated by urban block density and mean road width. We found that (1) both log-normal and gamma distributions can be good candidates for the size distribution of urban blocks at the scale of a region that consists of regular urban blocks and that has a uniform road width; and (2) the size distribution of urban blocks depends on the balance between pattern and width improvement effects. Based on one study region in Tokyo, if the pattern improvement effect is more prominent than the width improvement effect, the mode of urban block sizes tends to be larger than if it is not. These findings are expected to provide scientific support for urban planning (e.g. land readjustment projects).

Modern SoCs integrate multiple CPU cores and hardware accelerators (HWAs) that share the same main memory system, causing interference among memory requests from different agents. The result of this interference, if it is not controlled well, is missed deadlines for HWAs and low CPU performance. Few previous works have tackled this problem. State-of-the-art mechanisms designed for CPU-GPU systems strive to meet a target frame rate for GPUs by prioritizing the GPU close to the time when it has to complete a frame. We observe two major problems when such an approach is adapted to a heterogeneous CPU-HWA system. First, HWAs miss deadlines because they are prioritized only when close to their deadlines. Second, such an approach does not consider the diverse memory access characteristics of different applications running on CPUs and HWAs, leading to low performance for latency-sensitive CPU applications and deadline misses for some HWAs, including GPUs. In this article, we propose a Deadline-Aware memory Scheduler for Heterogeneous systems (DASH), which overcomes these problems using three key ideas, with the goal of meeting HWAs’ deadlines while providing high CPU performance. First, DASH prioritizes an HWA when it is not on track to meet its deadline any time during a deadline period, instead of prioritizing it only when close to a deadline. Second, DASH prioritizes HWAs over memory-intensive CPU applications based on the observation that memory-intensive applications’ performance is not sensitive to memory latency. Third, DASH treats short-deadline HWAs differently as they are more likely to miss their deadlines and schedules their requests based on worst-case memory access time estimates. Extensive evaluations across a wide variety of different workloads and systems show that DASH achieves significantly better CPU performance than the best previous scheduler while always meeting the deadlines for all HWAs, including GPUs, thereby largely improving frame rates.

New applications such as image recognition and augmented reality (AR) have become into practical on embedded systems. For these applications, we have developed a many-core SoC that includes two many-core clusters with 32 energy efficient processor cores connected by a low latency tree-based NoC. In this paper, we evaluate performance of many-core SoC by face detection as an example of real image recognition applications and discuss two parallelized implementations on the many-core clusters. By keeping balance of workloads on the cores, the performance scales up to 64 cores and the SoC consumes only 2.21W. The energy efficiency is several tens of times better than that of a high performance desk-top quad-core processor.

We developed a method that predicts the required number of cores for executing threads in the near future on a many-core processor. It is designed for low power consumption without performance degradation. The evaluation result confirmed the proposed method is effective on a 32-cores processor.

New media processing applications such as image recognition and AR (Augment Reality) have become into practical on embedded systems for automotive, digital-consumer and mobile products. Many-core processors have been proposed to realize much higher performance than multi-core processors. We have developed a low-power many-core SoC for multimedia applications in 40nm CMOS technology. Within a 210mm2 die, two 32-core clusters are integrated with dynamically reconfigurable processors, hardware accelerators, 2-channel DDR3 I/Fs, and other peripherals. Processor cores in the cluster share a 2MB L2 cache connected through a tree-based Network-on-Chip (NoC). Its total peak performance exceeds 1.5TOPS (Tera Operations Per Second). The high scalability and low power consumption are accomplished by parallelized firmware for multimedia applications. It operates the 1080p 30fps H.264 decoding about 400mW and the 4K2K 15fps super resolution under 800mW.