Image enhancement serves as a fundamental step in many advanced computer graphics tasks in the field of Internet of Things. However, existing methods often struggle to meet the demands of high-speed, high-resolution applications due to their high computational complexity, which heavily consumes the processor resources available on edge devices and limits their ability to support subsequent tasks. To address these challenges, this paper proposed the All-Channel Mean Spray Retinex (ACMSR) algorithm for the first time, which offers a more efficient and rapid solution for image enhancement. Furthermore, an in-situ computing ACMSR circuit is designed to eliminate the reliance on processor resources of edge devices. Compared to traditional methods, this circuit not only integrates sensing, storage, and computation in-sensor to execute the ACMSR algorithm, but also fully leverages the analog parallel computing capabilities of the memristor-crossbar-array circuit to perform architecture-level acceleration. Moreover, the proposed method achieves a processing speed of 69.3 FPS for 2K images. The circuit delivers output accuracy exceeding 98% under most types of interference.

Model Predictive Control (MPC), a receding-horizon optimal control strategy, predicts system dynamics and optimizes control actions to satisfy performance and constraint requirements, making it widely adopted in control engineering. However, contemporary computing platforms struggle to meet the real-time and energy-efficient demands of MPC’s computationally intensive matrix operations, stemming from high data movement overhead, extensive circuit resource utilization, and frequent data conversions inherent in physical system interfaces. These challenges collectively impose significant latency and power penalties, particularly critical as systems grow in complexity and scale within the big-data era. This article introduces a Zeroing Neural Network (ZNN)-based memristive neural network circuit that directly converges the MPC error function to zero in one step. Theoretical analysis and simulations validate the closed-loop circuit’s stability. For a 32-step prediction horizon, evaluations show that the control output from the proposed circuit matches the ideal digital MPC solution with 96.0% accuracy. The circuit also executes at least an order of magnitude faster and consumes less energy than traditional MPC solvers. Additionally, the circuit successfully accelerates the proposed trajectory tracking algorithm, achieving 98.0% accuracy compared with the theoretical result and 318.2× improvement in computation time compared to CPU.

Edge detection in images is the foundation of many complex tasks in computer graphics. Due to the feature loss caused by multi-layer convolution and pooling architectures, learning-based edge detection models often produce thick edges and struggle to detect the edges of small objects in images. Inspired by state space models, this paper presents an edge detection algorithm which effectively addresses the aforementioned issues. The presented algorithm obtains state space variables of the image from dual-input channels with minimal down-sampling processes and utilizes these state variables for real-time learning and memorization of image patches. To further enhance the processing speed of the algorithm, we have designed parallel computing circuits for the most computationally intensive parts of presented algorithm, significantly improving computational speed and efficiency. Simulation results demonstrate that the proposed algorithm achieves precise thin edge localization and exhibits noise suppression capabilities across various types of images. The parallel computing circuit achieves an output accuracy of over 92.13% under most interference conditions. Accelerated by this circuit, the calculation core of algorithm achieves a processing speed of 30fps on 5K images.

As a key kernel of matrix operation, lower–upper (LU) decomposition plays an important role in linear algebra and various engineering applications, such as deep learning and watermarking. Due to the complexity of large-scale matrix factorization, existing work mainly uses digital circuits and traditional computing architecture to realize LU decomposition, which inevitably faces the constraints of hardware resources and latency. Aiming at the above problem, this article first proposes the analog solver based on memristive arrays to realize LU decomposition of a nonsingular matrix in any dimension, with the advantages of high speed and parallel computing from analog circuits. The closed-loop circuit constructed therein endows it with excellent robustness and convergence characteristics during LU decomposition, and it can be performed in parallel. The simulation results indicate that the circuit designed for even 32nd-order LU matrix decomposition can achieve 95.90% accuracy. The accelerator achieved about$7\times$speed up on latency and$48.4\times$increase in TOPS performance compared to Alveo U50 FPGA, exhibiting superior performance in robustness and programming errors as well. Moreover, the proposed analog circuit serves to accelerate the embedding and extraction of digital watermarking based on LU decomposition, which enhances the invisibility of the watermark, and this application showcases the advantage of high accuracy and low energy consumption.

Quasi-cyclic moderate density parity-check McEliece (QMM) cryptosystem is designed to mitigate the security threat posed by quantum computers, and is considered to be a promising candidate for post-quantum cryptography (PQC). However, the growing requirement of data encryption pose severe challenges for QMM implementation in terms of latency and hardware overhead. In this work, we firstly propose ACIM-QMM, an analog computing-in-memory (CIM) accelerator design for QMM cryptosystem. The use of analog circuits and CIM enables the design to efficiently generate key and encrypt ciphertext while breaking the performance bottleneck constrained by digital computing paradigm in PQC. In the experiment, ACIM-QMM can work in low relative error, and it can achieve $31.4 \times \sim 288.1 \times$ speedup compared with SOTA hardware of QMM cryptosystem. Furthermore, the results indicate that ACIM-QMM can achieve a maximum of $3.12 \times$ area efficiency and $20.32 \times$ energy efficiency compared to other PQC hardware for 256-bit security.

Control systems play a crucial role in Internet of Things applications. However, in the face of increasingly complex physical environments and the sharp increase in data volume in edge computing scenarios, the transfer functions traditionally modeled through software methods tend to be offline processing. This limitation impedes the ability of Internet of Things device terminals to achieve real-time system monitoring and data analysis. In response to the challenge, this paper introduces a novel method for circuit modeling, which enables online simulation of any transfer function for the first time. Utilizing programmable memristors enables effective real-time control of system. This study validates the feasibility of the circuit modeling method by employing five engineering examples. Compared with MATLAB software modeling, the method in processing speed is at least 40 times faster and more prominent in the higher-order transfer function modeling, with a accuracy of 95.31%. Finally, this method is used to simulate an automotive cruise control system based on proportional-integral-derivative algorithm, which successfully realizes the real-time control and analysis of the dynamic behavior of the system, and also provides a new idea and technical path for the efficient and accurate dynamic management of Internet of Things systems in the future.

Riccati matrix equation (RME), a critical nonlinear matrix equation in autonomous driving and deep learning. However, memory-compute separation in traditional solving systems leads to latency and inefficiency when solving nonlinear equations, particularly under real-time requirements. Existing hardware lacks dedicated accelerators for RME, no specialized solvers quick addressing its nonlinear complexity. To address this issue, we propose a novel RME solver based on a memristive array, which leverages the parallel and fast computing advantages of analog circuits to quickly solve any order RME. Inspired by Neurodynamics for non-linear matrix equations, we first introduce an innovative Neurodynamics-based RME solving algorithm specifically designed from an analog circuit perspective. Based on this algorithm, we constructed a pioneering closed-loop analog circuit solver, overcoming bottlenecks in using circuits for such nonlinear matrix equations. Our evaluation demonstrates that the proposed solver achieves over 90% accuracy for a 128th-order parameter Riccati matrix equation. Compared to traditional digital processors, the solver offers significant energy efficiency advantages and is three orders of magnitude faster than CPU. Additionally, the solver successfully accelerates our proposed dung beetle optimizer-linear quadratic control algorithm for vehicle suspension control, achieving high precision while significantly reducing time and energy consumption compared to CPU and GPU.

The Oriented FAST and Rotated BRIEF (ORB) algorithm plays a crucial role in rapidly extracting image keypoints. However, in the domain of high-frame-rate real-time applications, the algorithm faces challenges of the speed and computational efficiency with the increase in both the size and quantity of images. To address this issue, an ORB algorithm accelerator based on a computing-in-memory (CIM) circuit is firstly proposed in this paper, which replaces the iterative calculations in traditional methods with one-step parallel analog computation. The proposed accelerator improves algorithm computational efficiency through CIM technology and enhances algorithm speed through parallel computation. Simulation demonstrate that the proposed method exhibits an average processing speed 22$\boldsymbol{\times}$faster than traditional methods and obtains more uniform corners distribution in large-scale images.

Kalman Filter (KF) algorithm, which can solve the state estimation problem of multi-variable and complex dynamical system, plays a pivotal role in a multitude of engineering scenarios. However, the traditional digital computing architecture represented by the von-Neumann architecture are currently confronted with high overhead challenges in terms of latency, energy, and area when executing KF algorithm. Aiming at the problem, we propose CIM-KF, the first Computing-in-memory (CIM) circuits for KF algorithm. CIM-KF can efficiently carry out the entire process of KF algorithm by capitalizing on the large-scale parallel computation inherent in the CIM architecture. The evaluation shows that CIM-KF has average 96.15% accuracy for 32-th order parameter matrix in KF algorithm, and can be 13.89 × ∼ 55.21 × faster than existing ASIC and FPGA implementations of KF algorithm. The results also demonstrate that CIM-KF can deliver up to 3.52 × energy efficiency improvement and 54.79 × area efficiency improvement, and reduce over 90% latency overhead, compared with the SOTA counterparts. Furthermore, we propose a novel design of ReRAM-CIM architecture, underpinned by the CIM-KF, aimed at precise and rapid calculation of the state of capacity and terminal voltage in Battery Management Systems. By evaluation, our proposed architecture boasts the estimation accuracy within 2% error for the individual battery cell of state of capacity and terminal voltage. With the strengths of the parallel computing intrinsic to CIM architecture and the speed of analog circuit, our architecture facilitates speed up to 70.6 × in accurate estimation when bench-marked against the SOTA work.

Memristive neuromorphic networks have great potential and advantage in both technology and computational protocols for artificial intelligence. Efficient hardware design of biological neuron models forms the core of research problems in neuromorphic networks. However, most of the existing research has been based on logic or integrated circuit principles, limited to replicating simple integrate-and-fire behaviors, while more complex firing characteristics have relied on the inherent properties of the devices themselves, without support from biological principles. This paper proposes a memristor-based neuron circuit system (MNCS) according to the microdynamics of neurons and complex neural cell structures. It leverages the nonlinearity and non-volatile characteristics of memristors to simulate the biological functions of various ion channels. It is designed based on the Hodgkin-Huxley (HH) model circuit, and the parameters are adjusted according to each neuronal firing mechanism. Both PSpice simulations and practical experiments have demonstrated that MNCS can replicate 24 types of repeating biological neuronal behaviors. Furthermore, the results from the Joint Inter-spike Interval(JISI) experiment indicate that as the background noise increases, MNCS exhibits pulse emission characteristics similar to those of biological neurons.

The limitations of traditional von Neumann architectures and digital computing are the bottlenecks for high-speed signal processing capabilities, not to mention the explosion of information growth. To tackle this challenge, this paper proposes an artificial neural network (ANN) equalizer based on the memristor for high-speed channel transmission at 112Gbps with 4-level pulse amplitude modulation (PAM4). To implement the PAM4 signal decision circuit based on the softmax algorithm, a comparator is used to make binary decisions for each output, and the only high-level output is further selected for the decision-making. The simulations on the PSPICE platform reveal that the number of input taps and the location of the main tap have the greatest impact on bit error rate (BER) performance. With optimal parameters, the circuit can achieve an impressive BER performance as low as 3.45E-6. To the best of our knowledge, this is the first implementation of channel equalization using memristive circuits, providing a valuable reference for analog circuit implementations of neural network equalizers.

As the core operation of lattice cipher, large-scale polynomial multiplication is the biggest computational bottleneck in its realization process. How to quickly calculate polynomial multiplication under resource constraints has become an urgent problem to be solved in the hardware implementation of lattice ciphers. Therefore, an analog in-memory circuit for fast polynomial multiplication calculation is proposed. First, an in-memory computing circuit for Discrete Fourier Transform and Inverse Discrete Fourier Transform based on memristor array is designed. On this basis, a fully analog circuit that can realize polynomial multiplication in one step is designed. Compared with traditional hardware implementation, the in-memory calculation method used in this article decreases the calculation time of polynomial multiplication to the microsecond level, which greatly improves the speed of lattice cipher encryption and decryption. For the specific examples in this article, PSPICE simulation shows that the average accuracy of the calculation result is above 99.90%.

Interference alignment can overcome the shortcomings in traditional interference management. How to quickly and efficiently eliminate interference by using interference alignment is an important question. Aiming at this problem, we propose an analog in-memory circuit based on memristors for accelerating the opposite directional interference alignment algorithm, which is achieved by solving complex-valued matrix equation and multiple complex-valued matrix multiplication. The circuits can adapt to any numbers of antennas condition and adjust the memconductance to map with the channel matrix in communication systems. The evaluation shows that the circuits not only have 99% high accuracy in executing a$2\times 2$channel state but also have good robustness against some nonideal factors from wireless communication that the corresponding accuracy can exceed 95% under the 10% noise impact. Moreover, the circuits accelerate the algorithm which is three orders of magnitude faster than software.

Matrix operations are widely used in practical engineering, but the traditional processing methods rely on the loop iterations and neural network algorithm on the software, requiring a long time to calculate. To address such problem, this paper proposes full hardware in-memory computing circuits based on programmable memristor unit array that can solve combinatorial matrix operations of any order in just one step. First, two basic circuit modules are introduced, which can respectively solve matrix multiplication and matrix equation. Further, the basic modules can be linked to solve combinatorial matrix operations with different forms. It’s worth noting that every module can parallel program the value of each memristor in the memristor unit array and complete one-step computation by hardware. Then, some matrix operations are given in the paper as examples to prove the high accuracy of proposed method, where the average accuracy rate achieves 99%. The PSPICE simulation results demonstrate that the processing speed is improved enormously according to the comparison of hardware and software. Moreover, the proposed method has broad application prospect in practical engineering, such as using designed combinational circuit to solve domain shift problem in zero-shot learning, which greatly accelerates the training process of zero-shot learning.

Equality-constrained quadratic programming (QP) has been one of the most basic and typical problems in the Internet of Things domain. In big data scenarios, how to quickly and accurately solve the problem in hardware has not been realized. Therefore, in this article, a memristive recurrent neural circuit that can parallel solve the QP problem in real time is proposed. First, a new memristive synaptic array is designed that can simultaneously implement parallel reading and writing. On the basis of this structure, a new neural network circuit based on memristor is designed that can perform large-scale recursive operations by parallel methods. This circuit can solve the equality-constrained QP problem in different situations by using such real-time programmable memristor arrays processing in memory. The PSpice simulation results show that the problem can be solved with 99.8% precision. Based on practical verification, the neural circuit experiment on PCB is presented with 97.34% precision. Moreover, the circuit has good robustness under the interference of weight value. And, it has an advantage in processing time compared with FPGA.

Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are core components in the field of signal processing. However, in the existing research, there is no fully analog circuit that can realize the one-step calculation of FFT. Therefore, in this paper, an analog circuit that can calculate FFT and its inverse transform IFFT in one-step is proposed. First, a circuit that can realize complex number operations is designed. On the basis of this structure, a fully analog circuit that can realize fast and efficient computing of FFT and IFFT in one-step is proposed. In addition, different coefficient matching can be obtained to achieve arbitrary points of FFT and IFFT by adjusting the resistance value of the memristor, which has good programmability. Specific examples are given in the paper to evaluate the proposed method. The PSPICE simulation results show that the average accuracy is above 99.98%. More importantly, the calculation speed has been greatly improved compared with MATLAB simulation. Finally, the proposed circuit can be used to quickly solve convolution operation, and the average accuracy can reach 99.95%.

In this paper, cluster synchronization on multiple nonlinearly coupled dynamical subnetworks of complex networks with nonidentical nodes and stochastic perturbations is studied. Based on the general leader-follower's model, an improved network structure model that consists of multiple pairs of matching subnetworks, each of which includes a leaders' subnetwork and a followers' subnetwork, is proposed. Moreover, the dynamical behaviors of the nodes belonging to the same pair of matching subnetworks are identical, while the ones belonging to different pairs of unmatched subnetworks are nonidentical. In this new setting, the aim is to design some suitable adaptive pinning controllers on the chosen nodes of each followers' subnetwork, such that the nodes in each subnetwork can be exponentially synchronized onto their reference state. Then, some cluster synchronization criteria for multiple nonlinearly coupled dynamical subnetworks of complex networks are established, and a pinning control scheme that the nodes with very large or low degrees are good candidates for applying pinning controllers is presented. Suitable adaptive update laws are used to deal with the unknown feedback gains between the pinned nodes and their leaders. Finally, several numerical simulations are given to demonstrate the effectiveness and applicability of the proposed approach.