In this paper, we propose a PE-based parallelism configurable polar encoder hardware architecture for emerging high-speed 5G communication system . This encoder architecture is applied to the 5G-NR PBCH channel polar encoder, implemented with functional modules such as CRC generation and interleaving, channel encoding, and rate matching as specified in the 3GPP protocol. Next, based on the united power format (UPF) low-power management technology, the PBCH polar encoder architecture is divided into different power domains based on their operating characteristics to reduce the power consumption . Experimental results show that the proposed polar encoder achieves throughput up to 30 Gbps. Based on TSMC 40 nm CMOS technology, by applying the proposed low-power methodology, the power consumption of the PBCH polar encoder at parallelisms of 8, 16, and 32 are 1.236 mW , 1.170 mW , and 1.084 mW , achieving power reductions of 24%, 29%, and 35% when comparing to non-low-power design, respectively.

As the development of 5G communications and Internet of things, more and more devices are required to run with low-power consumption and high performance as edge devices, and most of them have to do edge computing such as running the inference part of the artificial intelligence (AI) model to handle intelligent applications. In this paper, we deploy YOLOv3 and PPYOLO models on two kinds of intelligence edges, which are Jetson Nano and Jetson Xavier NX, to benchmark their performance. The tiny versions of YOLOv3 and PPYOLO are further deployed on Jetson Nano with relatively limited computing resources to make a comparative analysis. The benchmark results are analyzed and investigated to give empirical recommendation for reference of developing and deploying intelligent real-time object detection applications on intelligence edges to meet different requirements.

In this study, the authors address antenna selection (AS)‐aided massive multi‐user multiple‐input‐multiple‐output (MU‐MIMO) system based on maximum signal‐to‐noise ratio, where imperfect channel state information (CSI), time‐varying channel and antenna spatial correlation are considered. More explicitly, a computationally simple training‐based channel estimator is firstly employed for obtaining the imperfect down‐link CSI. Channel quantisation (CQ) is subsequently introduced by the feedback link which is used for feeding back so‐obtained CSI to base station. Time varying coefficient is utilised to characterise channel time variety and antenna spatial correlation is modelled by Kronecker model. Furthermore, the authors derive closed‐form ergodic channel capacity of the AS‐aided MU‐MIMO system with channel estimation error, CQ error and delay feedback, which has not yet been addressed in the state‐of‐the‐art approaches. Simulation results are provided to demonstrate the tightness of their theoretical computations of the ergodic channel capacity.

The birth of wireless communication systems nearly a century ago has transformed and redefined the way humans communicate and interact. This transformation has evolved over many years and has brought along not only seamless connectivity for human interactions but also communication between machines and devices. While these communication systems are manmade artifacts, the research community has more recently turned its attention to other communication strategies that have spontaneously evolved in nature.

The engineering vision of relying on the “smart sky” for supporting air traffic and the “internet-above-the-clouds” for in-flight entertainment has become imperative for the future aircraft industry. Aeronautical ad hoc networking (AANET) constitutes a compelling concept for providing broadband communications above clouds by extending the coverage of air-to-ground (A2G) networks to oceanic and remote airspace via autonomous and self-configured wireless networking among commercial passenger airplanes. The AANET concept may be viewed as a new member of the family of mobile ad hoc networks (MANETs) in action above the clouds. However, AANETs have more dynamic topologies, larger and more variable geographical network size, stricter security requirements, and more hostile transmission conditions. These specific characteristics lead to more grave challenges in aircraft mobility modeling, aeronautical channel modeling, and interference mitigation as well as in network scheduling and routing. This paper provides an overview of AANET solutions by characterizing the associated scenarios, requirements, and challenges. Explicitly, the research addressing the key techniques of AANETs, such as their mobility models, network scheduling and routing, security, and interference, is reviewed. Furthermore, we also identify the remaining challenges associated with developing AANETs and present their prospective solutions as well as open issues. The design framework of AANETs and the key technical issues are investigated along with some recent research results. Furthermore, a range of performance metrics optimized in designing AANETs and a number of representative multiobjective optimization algorithms are outlined.

This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order to constitute the proper interface between the VPDN and the DFT. The proposed logic can be easily implemented on-top of existing DFT solutions and its overhead is optimized by an algorithm that offers trade-off flexibility between test-application-time and hardware overhead. Through physical layout SPICE simulations, we show complete fault coverage recovery on stuck-open faults and 43.2% test-application-time improvement compared to a previously proposed DFT technique. To the best of our knowledge, this paper presents the first analysis of the VPDN impact on test quality.

SPICE offers an accurate method of simulating defect behavior. However, as demonstrated by recent research, it requires long computation time to simulate defect behavior, when considering process variation. To the best of our knowledge, there is no efficient variation-aware delay fault simulation methodology for resistive opens and resistive bridges. This paper presents a fast and accurate delay fault simulation methodology for these two defects. It is fast because it speeds up delay fault computation time by employing two efficient algorithms. The first algorithm is used to calculate transient gate output voltage, which is a key variable needed to compute delay faults. It employs a three step strategy to accelerate the computation of transient gate output voltage without compromising accuracy. The second algorithm uses bisection method to efficiently compute delay fault behavior of a fault-site. The proposed methodology (PM) has been incorporated in an open-source SPICE (NGSPICE) with BSIM4.7 transistor model. The methodology has been validated by comparing results with HSPICE using industrial designs from IWLS 2005 benchmarks and realistic fault-sites have been extracted from synthesized designs. Simulations are carried out using a 65-nm gate library (for illustration). When compared with HSPICE, results show that the PM is on average up to 52-times faster with ≤ 4.2% error in accuracy for resistive open and 39-times faster with ≤ 5.2% error in accuracy for resistive bridge defects.

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. Using transition delay test, this paper analyzes the behavior of resistive bridge defect under the influence of process variation. The effect of process variation is incorporated by using three transistor parameters: gate length (L), threshold voltage (Vth) and effective mobility (μeff), where each follows Gaussian distribution. Through HSPICE simulations using a 65-nm gate library, this paper brings the following two contributions: firstly, it analyzes the delay behavior of bridge defect using all three transition delay classes to determine the most effective class of transition test that achieves maximum coverage in the presence of process variation. Secondly, recent research has shown that low voltage testing improves detectability of bridge fault, this work compares bridge resistance coverage using logic test and delay test at multiple voltage settings to identify the best voltage setting and test type for detecting resistive bridge defects.

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present, there is no efficient device-level modeling technique that models the effect of process variation on resistive bridge defects. This paper presents a fast and accurate technique to achieve this, including modeling the effect of voltage and temperature variation using the BSIM4 transistor model. To speed up the computation time and without compromising simulation accuracy (achieved through BSIM4), two efficient voltage approximation algorithms are proposed for calculating logic threshold of driven gates and voltages on bridged lines of a fault-site to calculate bridge critical resistance. Experiments are conducted on a 65 nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 53 times faster and in the worst case, error in bridge critical resistance is 2.64% when compared with HSPICE.

Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is implemented in two stages: firstly, it employs an accurate transistor model (BSIM4) to calculate the critical resistance of a bridge; secondly, the effect of process variation is incorporated in this model by using three transistor parameters: gate length (L), threshold voltage (Vth) and effective mobility (μeff), where each follow Gaussian distribution. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 7 times faster and in the worst case, error in bridge critical resistance is 0.8% when compared with HSPICE.