While software testing is necessary for the production of quality products, it is generally one of the least efficient steps in the software development process. Testing typically consumes over 50 percent of the development effort. Software testing is thought of as an art and not a science, and artistic approaches to testing propagate the thinking. The complex test systems, complex program implementations, seemingly unrelated requirements and design information, and the complex system interactions all come to haunt and confuse the poor software developer when it comes time to certify the product is correct. In this document the authors have attempted to step back from all of these program intricacies and define what it means to test software programs. The authors then define a cause and effect testing methodology that integrates itself into the overall software development technique. Promising results are described from two development efforts that have used this approach for software testing.

Two addition and three multiplication algorithms were studied to see the effect of pipelining on system efficiency. A definition of efficiency was derived to compare the relative merits of various algorithms and implementations for addition and multiplication. This definition is basically defined as bandwidth/cost. Previous comparisons of adders and multipliers have generally been based on latency. In a pipeline environment, latency (or its Inverse bandwidth) is not as important. Any bandwidth is possible up to the physical limitations on gate delay variations and pulse skew. The formal definition for efficiency is: Efficiency = N / D · G where N is the number of bits in the operands, D is the delay (uniform) of each pipeline stage in units of gate delays and G is the total number of gates, including any used for latching. In cases where gate variations and pulse skewing are well defined pipelining using the Earle latch results in increased efficiency. The most efficient adder is a maximally pipelined conditional-sum adder (3 stages with a delay of 4 gates per stage). Its efficiency is 6.30×10-3. The most efficient multiplier is a maximally pipelined tree multiplier (8 stages with a delay of 4 gates per stage). It efficiency is 3.48×10-4.

Two addition and three multiplication algorithms were studied to see the effect of pipelining on system efficiency. A definition of efficiency was derived to compare the relative merits of various algorithms and implementations for addition and multiplication. This definition is basically defined as bandwidth cost. Previous comparisons of adders and multipliers have generally been based on latency. In a pipeline environment, latency (or its inverse bandwidth) is not as important. Any bandwidth is possible up to the physical limitations on gate delay variations and pulse skew. The formal definition for efficiency is efficiency = N/D·G where N is the number of bits in the operands, D is the delay (uniform) of each pipeline stage in units of gate delays, and G is the total number of gates, including any used for latching. In cases where gate variations and pulse skewing are well defined, pipelining using the Earle latch results in increased efficiency. The most efficient adder is a maximally pipelined conditional-sum adder (three stages with a delay of four gates per stage). Its efficiency is 6.30×10-3. The most efficient multiplier is a maximally pipelined tree multiplier (eight stages with a delay of four gates per stage). Its efficiency is 3.48×10-4.