This paper proposes a threat detection system based on Machine Learning classifiers that are trained using darknet traffic. Traffic destined to Darknet is either malicious or by misconfiguration. Darknet traffic contains traces of several threats such as DDoS attacks, botnets, spoofing, probes and scanning attacks. We analyse darknet traffic by extracting network traffic features from it that help in finding patterns of these advanced threats. We collected the darknet traffic from the network sensors deployed at SURFnet and extracted several network-based features. In this study, we proposed a framework that uses supervised machine learning and a concept drift detector. Our experimental results show that our classifiers can easily distinguish between benign and malign traffic and are able to detect known and unknown threats effectively with an accuracy above 99%.

LoRaWAN is the dominant protocol for communication in low-power Wide Area Networks in several European countries, and is being used increasingly in other parts of the world. We identified three vulnerabilities in the LoRaWAN protocol specification that can be used for launching Denial-of-Service (DoS) attacks against end-devices in a LoRaWAN network. We validated that these vulnerabilities can be exploited for DoS attacks by creating and simulating Coloured Petri Net models of relevant parts of the LoRaWAN protocol.

We present a novel method for static analysis in which we combine data-flow analysis with machine learning to detect SQL injection (SQLi) and Cross-Site Scripting (XSS) vulnerabilities in PHP applications. We assembled a dataset from the National Vulnerability Database and the SAMATE project, containing vulnerable PHP code samples and their patched versions in which the vulnerability is solved. We extracted features from the code samples by applying data-flow analysis techniques, including reaching definitions analysis, taint analysis, and reaching constants analysis. We used these features in machine learning to train various probabilistic classifiers. To demonstrate the effectiveness of our approach, we built a tool called WIRECAML, and compared our tool to other tools for vulnerability detection in PHP code. Our tool performed best for detecting both SQLi and XSS vulnerabilities. We also tried our approach on a number of open-source software applications, and found a previously unknown vulnerability in a photo-sharing web application.

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Supporting students with feedback and guidance while they work on networking exercises can be provided in on-campus universities by human course advisors. A shortcoming however is that these advisors are not continuously available for the students, especially when students are working on exercises independently from the university, e.g. at home using a virtual environment. In order to improve this learning situation we present our concept of an exercise assistant, which is able to provide feedback and guidance to the student while they are working on exercises. This exercise assistant is also able to verify solutions based on expert knowledge modelled using description logic.

Modern technology offers the tools for having synchronous virtual classes. This paper reports about experiences of such a class in the context of distance education. The paper focuses on the tool as well as on the pedagogy. It outlines the pedagogical approach of the virtual class, which is an adaptation of good practices of face-to-face classes. The results of an experiment are discussed. Strong and weak aspects of synchronous virtual classes are identified.

This paper shows that accurate fault detection and diagnosis are possible when applying a parity tree for space compaction of test responses and continuously observing the parity-tree output. We exploit that each set of faults results in a unique parity-tree output sequence that can be used as a unique fault signature for truly accurate fault detection and diagnosis. Our theoretical analysis shows that probabilities for fault cancellation and fault aliasing are extremely low and decrease with circuit size. Experimental results show that for a typical scan chain architecture in large industrial circuits, fault coverage is not affected by parity-tree space compaction for up to 256 scan chains, while diagnostic resolution is reduced by only 1% to 2%.

This paper presents an experimental investigation on the impact of test point insertion on circuit size and performance. Often test points are inserted into a circuit in order to improve the circuit's testability, which results in smaller test data volume, shorter test time, and higher fault coverage. Inserting test points however requires additional silicon area and influences the timing of a circuit. The paper shows how placement and routing is affected by test point insertion during layout generation. Experimental data for industrial circuits show that inserting 1% test points in general increases the silicon area after layout by less than 0.5% while the performance of the circuit may be reduced by 5% or more.

Deterministic logic BIST (DLBIST) is an attractive test strategy, since it combines advantages of deterministic external testing and pseudo-random LBIST. Unfortunately, previously published DLBIST methods are unsuited for large ICs, since computing time and memory consumption of the DLBIST synthesis algorithms increase exponentially, or at least cubically, with the circuit size. In this paper, we propose a novel DLBIST synthesis procedure that has nearly linear complexity in terms of both computing time and memory consumption. The new algorithms are based on binary decision diagrams (BDDs). We demonstrate the efficiency of the new algorithms for industrial designs up to 2M gates.

We present a technique for making a circuit ready for logic BIST by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at n-detection based metric, such that the impact of masking on the defect coverage is minimal. An analysis based on a probabilistic model for resistive short defects indicates that the coverage loss for unmodeled defects is negligible for relatively low values of n.

paper presents an approach for reducing the test data volume that has to be stored in ATE vector memory for IC manufacturing testing. We exploit the capabilities of pre- sent ATE to assign groups of input pins to ports and to perform vector repeat per port. This allows run-length encoding of test stimuli per port. We improve the encoding byjlling the don't-care bits in the test stimuli, such that longer run-lengths are obtained. We provide a probabilis- tic analysis of the performance of vector repeat per port with various ATPG padding types. We further discuss the impact of ATE architectures. The paper provides experi- mental data for a set of large industrial circuits, which shows an average reduction of the test stimulus data vol- ume by a factor of 13.

A divide-and-conquer approach using circuit partitioning is presented, which can be used to accelerate logic BIST synthesis procedures. Many BIST synthesis algorithms contain steps with a time complexity which increases more than linearly with the circuit size. By extracting sub-circuits which are almost constant in size, BIST synthesis for very large designs may be possible within linear time. The partitioning approach does nor require any physical modifications of the circuit under test. Experiments show that significant performance improvements can be obtained at the cost of a longer test application time or a slight increase in silicon area for the BIST hardware.

This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-PPCT for full-scan design, as well as for full-scan core-based design.

We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.

We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a core, its design must be supplemented with on-chip co-processors to obtain a cost-effective system. Good performance is obtained through a uniform 64-bit 5 issue-slot VLIW design, supporting subword parallelism with an extensive instruction set optimized with respect to media-processing. Multi-slot 'super-ops' allow powerful multi-argument and multi-result operations. As an example, the IDCT algorithm shows a very low instruction count in comparison with other processors. To achieve good performance, critical sections in the application program source code need to be rewritten with vector data types and function calls for media operations. Benchmarking with several media applications was used to tune the instruction set and study cache behaviour. This resulted in a VLIW architecture with wide data paths and relatively simple CPU control.

As modern digital hardware/software systems become more complex, the testing of these systems throughout their entire system life cycle, including design verification, production testing, and field testing, becomes a severe problem. In this paper a structured approach is presented to solve the problems of system-level testability. A strategy towards design for system-level testability is introduced, which consists of partitioning the system specification into testable parts, and inserting implementation-independent test functionality in the specification. Incorporating these test requirements in the hardware/software implementation will considerably improve system-level testability. The design and implementation of a traffic-lights control system is presented as an example to illustrate the benefits of this approach.