VLDB 2026 Research / reviewers in the wild / expert
Michael I. Parr
dblp:13/1715
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › parallel algorithms › parallel matrix algorithms
parallel sparse factorization |
0.0 | 1 | 1983 | An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix Equations · IEEE Trans. Computers 1983 |
Parallel and multicore computing › multiprocessor system
MIMD multiprocessor |
0.0 | 1 | 1983 | An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix Equations · IEEE Trans. Computers 1983 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.0bus contention modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix EquationsabstractAn algorithm for the parallel solution of large sparse sets of linear equations, given their factor matrices, is developed. It is aimed at efficient practical implementation on a processor of the multiple instruction multiple data stream (MIMD) type. The software required to implement the algorithm is described. In addition, the amount of memory necessary for data retention during execution is considered and related to that which is required on single processor systems. Hardware developed for the implementation of the algorithm is described. Bus contention for the system is outlined and shown to be insignificant. Possible bus contention problems for systems differing in the number of processors and speed of processing elements are also considered. A simulator modeling the execution of the algorithm on large systems has been implemented. The performance of the algorithm, in terms of execution speed enhancement relative to the theoretical maximum, is shown to be good. Christopher P. Arnold, Michael I. Parr, Michael B. Dewe |
IEEE Trans. Computers | 2 |