Image and signal processing workloads are widely deployed on Graphics Processing Units (GPUs) for high throughput and on Field-Programmable Gate Arrays (FPGAs) for hardware specialization and energy efficiency. Soft GPU overlays on FPGAs aim to combine these advantages, yet existing solutions often depend on fixed hard processors or impose platform constraints that limit portability. This work extends a popular open-source soft GPGPU overlay to integrate a soft RISC-V control plane and enable compatibility with High-Bandwidth Memory (HBM2). The resulting system can be instantiated on FPGA boards without a hard ARM processor, improving portability, simplifying system integration, and broadening deployability. Across representative image and signal processing kernels, the soft GPGPU achieves geometric-mean speedups of 114.60 × over a scalar soft RISC-V core and 19.72 × over a hard ARM core, demonstrating substantial performance benefits while retaining FPGA reconfigurability. HBM2 integration further benefits bandwidth-sensitive workloads by increasing sustained throughput and reducing the performance bottlenecks associated with off-chip memory access. Collectively, these results indicate that GPU-like programmability and performance can be delivered on reconfigurable platforms without reliance on hard CPU subsystems, providing a portable and scalable foundation for embedded vision and DSP acceleration.

The increasing use of deep neural network (DNN) based applications on edge devices has driven the need for innovative computing solutions that can meet the high computational requirements of DNN workloads while ensuring low power consumption. Therefore, enhancing the general-purpose (GP) computing units of edge devices by integrating DNN-specific functions and operations into existing instruction set architectures (ISAs) provides the flexibility to support a wide variety of neural network models, thereby improving computing efficiency. This article proposes a programmable tightly coupled accelerator for convolution operations called ProCon-V. It is based on RISCV custom instructions, extending the standard ISA to support 2-D convolution operations. The accelerator is tightly coupled with a RISC-V-based pipeline through an open-source extension interface [21], offloading convolution operations from the pipeline’s main execution unit. The ProCon-V computing engine is based on a scalable systolic array architecture for partial-sum computation, with hardware-supported Im2Col transformation that supports multi-channel convolution layers with various configurations. Moreover, the tightly coupled accelerator enables the execution of convolution layers through a set of custom instructions handled by the RISC-V core without requiring extra modifications to the core pipeline. ProCon-V is implemented and evaluated on an AMD/Xilinx Virtex Ultrascale+ FPGA featuring dual clock domains for the RISC-V core and the convolution accelerator. Evaluation results demonstrate that the proposed accelerator features a maximum computing throughput of 174.4 GOPS for INT8-based operations with an energy efficiency of 181.7 GOPS/W.

Since dynamic power has a quadratic relationship with voltage, reducing voltage is an effective way to lower power consumption in digital circuits. However, maintaining stable operation at lower voltages is challenging due to increased sensitivity to Process, Voltage, and Temperature (PVT) variations, making it difficult to determine optimal operating points using Static Timing Analysis (STA). While circuit-and device-level solutions like Timing Error Detection (TED) systems can enable lower voltage operation, they introduce significant overhead and design complexity. In this paper, we integrate an Algorithm-Based Fault Detection (ABFT) method into the structure of systolic arrays to capture timing errors when voltage is scaled down, ensuring safe and optimized low-voltage operation. Our proposed approach, SCISSORS, demonstrates how extra voltage margins in systolic arrays used for matrix arithmetic can be trimmed by integrating a simple algorithmic technique into the structure of the array. This solution not only detects errors in the accelerator but also those caused by voltage reduction in on-chip memory and auxiliary circuits. It is fully implementable through HDL without requiring transistor-or circuit-level modifications to the netlist. Implementation on a Zynq System-on-Chip (SoC) shows that SCISSORS introduces only a tolerable overhead of 11% and 8% for 32×32 and 64×64 systolic arrays, respectively, while achieving nearly a 2× improvement in energy efficiency. Experimental results further demonstrate that SCISSORS adaptively adjusts voltage in response to the voltage-temperature coupling behavior of digital circuits at runtime, specifically addressing Inverse Temperature Dependence (ITD).

ORB-SLAM3 is a state-of-the-art visual SLAM system, but its computational complexity poses major challenges for real-time deployment on embedded platforms. While prior work has largely focused on accelerating front-end tasks like feature extraction, back-end stages such as bundle adjustment remain less explored due to their algorithmic complexity and memory-intensive nature. Furthermore, most existing solutions accelerate specific modules without integrating them into a complete SLAM framework. In this work, we present SoC-SLAM, a novel FPGA-based hardware/software co-design that accelerates both the front-end and back-end stages of ORB-SLAM3 within a unified framework. Profiling identifies ORB feature extraction and local bundle adjustment as the primary performance bottlenecks, both critical for maintaining real-time system responsiveness. To address these, we develop modular FPGA-based accelerators for ORB extraction and key bundle adjustment solver steps, including Schur elimination, Cholesky decomposition, and back substitution, while retaining the remaining pipeline in software. Since the workload predominantly consists of operations on sparse block matrices, we develop and combine several optimization techniques, including matrix partitioning and pipelined block processing, to efficiently handle sparsity and maximize parallelism. Evaluation on the EuRoC MAV dataset shows $8 \times$ and $7.4 \times$ speedups for ORB extraction and local bundle adjustment, resulting in $2.4 \times$ and $3.3 \times$ improvements in the Tracking and Local Mapping threads, respectively. The system operates at 222 MHz, consumes 4.276 W, and achieves an RMSE of 0.02832 m. Our fully integrated pipeline demonstrates competitive performance and power efficiency compared to prior FPGA, ASIC, and GPU-based solutions. The proposed architecture is scalable and generalizable to other bundle adjustment modules, such as global bundle adjustment, welding bundle adjustment, and essential graph optimization, offering an extensible hardware acceleration design for real-time visual SLAM on resource-constrained platforms.

Robot systems are facing a growing demand for realtime performance of multiple computing tasks and autonomous decision-making. However, limited computing resources make efficient scheduling of computing tasks and optimizing resource utilization a key challenge. Virtualization of field-programmable gate arrays enables the dynamic sharing of hardware resources, while dynamic partial reconfiguration allows for flexible adjustment of hardware accelerators based on task requirements, making it suitable for complex and fluctuating computing loads. However, virtualization scheduling based on operating systems or microkernels usually introduces high software overhead. This paper proposes a hardware-level adaptive scheduling mechanism integrated with spatiotemporal scheduling to efficiently share reconfigurable computing resources among multiple users. This mechanism is transparent to users and can adaptively adjust the spatiotemporal allocation strategy according to the characteristics of tasks. In addition, the scheduling scheme introduces access rights management to strictly prevent unauthorized resource access. Hardware scheduling system achieves a speedup of over $1000 \times$ compared to a software-based scheduling system when executing 100 hardware tasks, reducing execution time from seconds to milliseconds.

The escalating demand for energy-efficient embedded systems necessitates innovative approaches to mitigate dynamic power consumption in general-purpose cores. This paper introduces a threshold-based, workload-adaptive clockgating technique for a dual-issue RISC-V core, dynamically disabling the underutilized second-issue datapath to reduce dynamic power consumption. The method employs a threshold-based clock-gating controller that dynamically activates the secondissue pipeline according to the target workload and desired energy/performance trade-offs. By integrating latch- and flip-flop-based clock-gating mechanisms into the open-source VeeR EH1 dual-issue core, coarse-grained control over the secondissue pipeline is achieved, enhancing energy efficiency with minimal impact on computing performance. For prototyping and evaluation, an FPGA implementation targeting AMD/Xilinx FPGA devices, along with CoreMark benchmark evaluation, has been conducted, demonstrating 5% improvement in energy efficiency and a dynamic power savings of up to 15%, making the approach particularly suitable for power-constrained embedded systems.

GEMM (General Matrix Multiplication) is a fundamental operation in deep learning (DL), serving as the key computing kernel for neural network layers, such as convolutional and fully connected layers. As the deployment of DL models expands beyond high-performance computing to resource-constrained embedded systems, there is a growing demand for efficient GEMM implementations that can meet strict power budgets and real-time processing requirements. This paper introduces a dual-issue in-order RISC-V core with an inpipeline GEMM accelerator based on the VeeR EH1 core [13], eliminating control signals and data transfer overhead inherent to coprocessors and standalone accelerators. By integrating GEMM execution directly into the pipeline, the design leverages core utilization and enables compiler-time preloading of operands, streamlining memory access and reducing dynamic branching, thereby minimizing branch mispredictions. Further, pipelined load/store operations mitigate memory access stalls and cache misses, thereby enhancing the pipeline throughput. Speedup, measured using Verilator simulation, demonstrates an average of$\sim 5 \times$over the reference VeeR EH1 baseline core. By integrating GEMM acceleration within the pipeline, this work bridges the gap between domain-specific accelerators and general-purpose cores, delivering scalable computing performance.

Domain-specific accelerators on Field-Programmable Gate Arrays (FPGAs) have been identified as one potential solution to continue the performance scaling after Moore’s Law ends. However, the design of such accelerators is cumbersome, leading to limited productivity and reduced adoption rates, especially in heterogeneous FPGA systems. Thus, this survey investigated hardware design approaches suited for heterogeneous system developers. High-Level Synthesis (HLS) has been identified as the most fitting category for this objective. Currently, we see the creation of many new HLS-related tools that are hard to classify according to conventional taxonomies. Therefore, this work establishes an explicit definition for HLS approaches based on intended usage. The definition combines the classification of hardware design abstractions with parallel programming models to identify suitable approaches unambiguously. The resulting HLS-related tools are categorized and presented according to a newly developed taxonomy. This taxonomy unifies the current vast ecosystem of HLS-related frameworks, including conventional HLS tools as Backends, embedded Domain Space Exploration (DSE) approaches and system-level integrating tools.

By moving data and computation away from the end user to more powerful servers in the cloud or to cloudlets at the edge, end user devices only need to compute locally for small amounts of data and when low latency is required. However, with the advent of 6G and Internet-of-Everything, the demand for more powerful networks continues to grow. The introduction of Software-Defined Networking and Network Function Virtualization has allowed us to rethink networks and use them for more than just routing data to servers. In addition, the use of more powerful network devices is bringing new life to the concept of active networks in the form of in-network computing. In-Network Computing provides the ability to move applications into the network and process data on programmable network devices as they are transmitted. In this work, we provide an overview of in-network computing and its enabling technologies. We take a look at the programmability and different hardware architectures for SmartNICs and switches, focusing primarily on accelerators such as FPGAs. We discuss the state of the art and challenges in this area, and look at CGRAs, a class of hardware accelerators that have not been widely discussed in this context.

We present a way of failure detection in real-time unmanned aerial vehicles (UAVs) by integrating Chaos Theory and AI techniques on an FPGA board. The Signal Analysis based on Chaos using the Density of Maxima (SAC-DM) validates the input of the Machine Learning (ML) model due to the relation between the density of maxima and autocorrelation length. While the accuracies achieved solely by SAC-DM are not remarkably high, the ML model demonstrates an accuracy of 92.46% when utilizing sac-dm results as inputs. The unprecedented integration of SAC-DM on FPGA board serves as a solution for high-speed onboard processing, parallel integrated data synchronization and fusion, and an enhanced low-power architecture.

Coarse-Grained Reconfigurable Architectures (CGRAs) are one of the promising solutions to be employed in power-hungry edge devices owing to providing a good balance between reconfigurability, performance and energy-efficiency. Most of the proposed CGRAs feature a homogeneous set of processing elements (PEs) which all support the same set of operations. Homogeneous PEs can lead to high unwanted power consumption. As application benchmarks utilize different operations irregularly, heterogeneous PE design is a powerful approach to reduce power consumption of CGRA. In this paper, we propose DA-CGRA, a domain-aware CGRA tailored to signal processing applications. To extract heterogeneous architecture, first, a set of signal processing applications has been profiled to derive the requirements of the applications in terms of type of operations, number of operations and memory usage. Then, domain-specific PEs are designed using Verilog RTL based on the profiling results. We have selected spatio-temporal or spatial execution model based on the application features to increase the overall performance and efficiency. Experimental results demonstrate DA-CGRA outperforms FLEX and RipTide state-of-the-art CGRAs in terms of energy-efficiency by 23% and 38%, respectively. Moreover, DA-CGRA can achieve 3.2x performance improvement over HM-HvCUBE.

With the trend to consolidate hardware on a single platform, FPGA virtualization plays an increasingly important role in the embedded domain. FPGA virtualization allows multiple software tasks or even guest operating systems to share recon- figurable resources. However, state-of-the-art approaches assign each hardware accelerator to a single software task for a fixed duration. This becomes a problem when the number of hardware accelerators required by software tasks concurrently exceeds the FPGA area. If several software tasks request to accelerate the same functionality, accelerators can be shared. Embedded reconfigurable systems face the challenge of a uniform address space. When several tasks use a memory-mapped communication interface that allows to directly access the accelerator's address space, access control and the protection from unauthorized access must be ensured. Existing software-based approaches lead to high latencies. Thus, we propose a hardware-level scheduler that schedules hardware tasks in spatial and temporal respect. The allocation to a hardware accelerator is combined with the assignment of access rights. Any unauthorized access leads to a page fault. When hardware tasks share an accelerator, they are scheduled according to the Earliest Deadline First (EDF) policy. Buffers ensure data isolation. Compared to hardware task scheduling in software, a performance increase of 7.02 times is reached.

Dynamic Voltage and Frequency Scaling (DVFS) is an effective means to reduce the energy dissipation of digital designs. While on most commodity FPGAs, memory and processor have separately controlled voltages, the programmable logic section relies on a single voltage rail and thus imposes the same voltage for all hardware accelerators that operate concurrently. Finding time slots eligible for voltage scaling gets difficult in virtualized systems, where the FPGA is shared by tasks executed in multiple guest operating systems. The situation gets even more complicated, when error-tolerant tasks are considered that allow the voltage to be reduced below its nominal value, which could provoke a certain rate of faulty hardware accelerator runs. As a solution, we propose a strategy that synchronizes concurrently executed periodic hardware tasks under consideration of their reliability as well as their real-time requirements so that the supply voltage is controlled accordingly. The proposed strategy can be combined with further mechanisms for saving energy. Our run-time module performs clock gating and adjusts the voltage to the requirements of aperiodic tasks. For fault-tolerant tasks, we monitor the error rate using Algorithm Based Fault Tolerance (ABFT) that can detect and characterize errors with an accuracy close to $100 \%$. Compared to a strategy that scales voltage without synchronizing hardware tasks, we achieve in the best case a power saving by $29.4 \%$ and an average saving by $7 \%$.

The terahertz (THz) spectrum, with its abundant available bandwidths, has garnered significant attention for its potential to advance wireless communications and enhance radar sensing capabilities, leading to improved data rates and spatial resolution, respectively. However, in indoor environments, the blockage or significant attenuation of THz waves due to the presence of humans and other obstructing materials poses a recognized challenge. Therefore, a line-of-sight (LoS) link is preferred though cannot be guaranteed in all situations. Nonetheless, this work explores the scattering properties of commonly encountered indoor objects, such as walls, for establishing a nonline-of-sight (N-LoS) link. An N-LoS testbed is employed to investigate both the communications and radar sensing capabilities through wall reflections. From a communications perspective, the recording of the transmit signal at varying incidence angles is presented. Additionally, radar imaging is demonstrated employing the syn-thetic aperture radar (SAR) technique, enabling the visualization of objects hidden from direct view.

The International Conference on Field-Programmable Logic and Applications (FPL) was the first and remains the largest conference covering the rapidly growing area of field-programmable logic and reconfigurable computing.During the past 30 years, many of the advances in reconfigurable system architectures, applications, embedded processors, and design automation methods and tools were first published in the proceedings of the FPL conference series.The conference objective is to bring together researchers and practitioners from both academia and industry and from around the world.The 31st edition of the FPL (2021) took place from August 30 till September 3, 2021.It is the second FPL conference that had to be organized as a virtual event due to the COVID-19 pandemic.The purpose of this Special Section is to provide an insight into current research and development in aspects related to Field-Programmable Gate Array (FPGA) applications, FPGA technology, and FPGA programming models and tools.This Special Section includes three papers that were presented in the 2021 edition of the conference.The three articles were appropriately selected (based on their quality) to cover various topics of the conference.

As runtime reconfiguration is used in an increasing number of hardware architectures, new simulation and modeling tools are needed to support the developer during the design phases. In this article, a language extension for SystemC is presented, together with a design methodology for the description and simulation of dynamically reconfigurable hardware at different levels of abstraction. The library presented offers a high degree of flexibility in the description of reconfiguration features and their management, while allowing runtime reconfiguration simulation, removal, and replacement of custom modules as well as third-party components throughout the architecture development process. In addition, our approach supports the emerging concept of nested reconfiguration and split regions with a minimal simulation overhead of a maximum of three delta cycles for signal and transaction forwarding, and four delta cycles for the reconfiguration process.

The computational complexity of Nonlinear Model Predictive Control (NMPC) often hinders their application to cyber-physical systems with fast dynamics, such as mobile robots or Unmanned Aerial Vehicles. This complexity overhead comes from the control algorithm's backbone, an iterative solver that must ensure convergence and often takes the form of a highly structured convex Quadratic Program (QP). Such overhead could be overcome using specialized computer architectures. Field Programmable Gate Arrays are good candidates for making hardware accelerators that comply with the realtime constraints of fast-dynamic cyber-physical systems. Nevertheless, QP-solvers have been demonstrated to be complex to implement as a hardware accelerator. With this in mind, the present paper proposes a novel accelerator architecture that uses Knowledge-based Particle Swarm Optimization (PSO) as a solver while exploring its parallel nature. PSO is a stochastic global optimization algorithm that creates a fast and precise solution for NMPC. The proposed strategy in this papergrants system control stability for short sampling frequencies and long prediction horizons. It can also meet realtime constraints while achieving low hardware consumption. Additionally, it is generalized, so it can potentially be adapted to any application and is compatible with the Robot Operating System (ROS). The architecture is tested with two applications: an inverted pendulum swing-up procedure and a quadrotor drone with control and state constraints. Following, we analyze the accelerator performance and highlight our solution's advantages to other works in the literature. Namely, our architecture solves more complex problems with a greater dimension and longer horizon while using similar resources. The proposed solution also has good computational performance (29ms and 11ms) for both the quadrotor and inverted pendulum, respectively, while achieving the realtime requirements (50ms and 100ms, respectively). Parallelly, ad-hoc embedded architectures are important for a low-end, low-cost, and low-power MPSoC+FPGA device. Our solution uses less than 50% of a low-end, low-power MPSoC device (ZU3EG), while others rely on large, more power-hungry devices (e.g., Kintex7 and XC7Z045).

The EuFRATE project aims to research, develop and test radiation-hardening methods for telecommunication payloads deployed for Geostationary-Earth Orbit (GEO) using Commercial-Off- The-Shelf Field Programmable Gate Arrays (FPGAs). This project is conducted by Argotec Group (Italy) with the collaboration of two partners: Politecnico di Torino (Italy) and Technische Universität Dresden (Germany). The idea of the project focuses on high-performance telecommunication algorithms and the design and implementation strategies for connecting an FPGA device into a robust and efficient cluster of multi-FPGA systems. The radiation-hardening techniques currently under development are addressing both device and cluster levels, with redundant datapaths on multiple devices, comparing the results and isolating fatal errors. This paper introduces the current state of the project's hardware design description, the composition of the FPGA cluster node, the proposed cluster topology, and the radiation hardening techniques. Intermediate stage experimental results of the FPGA communication layer performance and fault detection techniques are presented. Finally, a wide summary of the project's impact on the scientific community is provided.1

Coarse-Grained Reconfigurable Architectures (CGRAs) are promising solutions to achieve more performance with the end of Moore's law. CGRAs can provide flexibility as well as near-ASIC energy efficiency. Since the advent of IoT and battery-powered edge devices, energy efficiency is becoming increasingly important. Memory accesses contribute to about 50% of overall energy consumption of the CGRAs. Interesting features of emerging non-volatile memories (eNVMs) like low power consumption and high density have grown the attentions. In this work, the effect of eNVMs on energy efficiency of CGRAs have been investigated. The analysis using Polybench benchmark suite shows that STT-MRAM and PCM can result in a 94 % and 85 % reduction of energy consumption of memory accesses respectively compared to SRAM. Moreover, total access latency can also be improved by 60% and 49% in STT-MRAM and PCM.

In an ever-evolving digital world with complex algorithms like machine learning, we need new strategies for more flexibility to cope with the ever-changing environment. For this, runtime scalability and runtime adaptability for low-power and highly efficient hardware is a promising solution. By combining the runtime reconfiguration of FPGAs with the efficient communication of Networks-on-Chip (NoC), we are able to implement a highly scalable, high-performance, and energy-efficient computing architecture that fixed-function units and specialized static accelerators lack. In this work, we introduce a RunTime Adaptable and Scalable System for NoC-based architectures called RTASS. The hardware architecture includes a master subsystem, a network adapter, and an NoC subsystem with parametrizable routers and several various routing algorithms. Furthermore, RTASS provides a software architecture that includes advanced drivers for runtime management. The key benefit of RTASS is the ability to dynamically adjust the number of routers within the NoC at runtime based on the current application's requirements. That allows the system to support both homogeneous and inhomogeneous types of processing elements as well as regular and irregular shapes. The development of this runtime scalable and flexible architecture will establish the foundation for future highly adaptable applications such as machine learning and computer vision in the embedded computing field. We implemented and evaluated the proposed work with the Xilinx Zynq-7000 FPGA, with the possibility of porting it to other FPGAs that support runtime reconfiguration.

The bandwidth improvement provided by high-bandwidth memory (HBM), and the capability of FPGAs to customize the processing and memory hierarchy, results in a considerable performance increase for memory-intensive work-loads such as graph processing, sorting, machine learning, and database analytics. Modern systems integrating 3D-stacked DRAM memory can be leveraged to realize the Near-Memory Computing (NMC) paradigm by offloading some computations to accelerators placed near the HBM. Although numerous studies have investigated efficient accelerators for FPGA-HBM platforms, researchers have not proposed a systematic way for identifying which application kernels are suitable for execution near the HBM. In this article, we propose compiler support for recognizing offloading candidates without any burden on programmers. Auto-DOK analyzes an application code based on criteria derived from the hardware design goals of FPGA-HBM platforms, and automatically identifies kernels suitable for offloading. We evaluate Auto-DOK on benchmarks ranging from microbenchmarks to real-world kernels. Our results show that Auto-DOK can correctly identify kernels and input sizes suitable for execution near the HBM, and prevents slowdown caused by incorrect offloading decisions for other workloads. Moreover, Auto-DOK operates at compile time with negligible overhead and without the need for expensive profiling.

Networks-on-Chip (NoCs) are beneficial for reconfigurable systems that require a high degree of parallel and scalable communication. NoCs are reusable as hardware accelerators can be exchanged via dynamic partial reconfiguration. Nevertheless, NoCs are not conceptualized for the use in a virtualized environment where applications from multiple virtual machines have to share reconfigurable resources. Many state-of-the-art works assign hardware accelerators exclusively to a single virtual machine, which limits the number of processed hardware tasks and leads to underutilization of FPGA area. Therefore, we provide a NoC virtualization layer that allows the execution of several pipelined hardware tasks agnostic of the location of the required hardware accelerators. The allocation of tasks to processing elements can be adapted to dynamically changing requirements, while unauthorized access is prohibited. Further, we provide a scheduler that schedules hardware tasks in spatial and temporal respect to processing elements in the NoC. The proposed heuristic considers task priorities, a possible reuse of accelerators and hop counts. In over-load conditions, the tasks with the lowest priorities are postponed. Our virtualization layer increases the number of tasks processed by 22.6% compared to an approach that grants exclusive access.

The speed of modern computing systems has improved significantly, thanks to advances in CMOS technology. However, the memory bandwidth of DRAM has not kept pace with these improvements in terms of latency and energy consumption, which is known as the memory wall [1]. FPGAs with high-bandwidth memory (HBM) provide significantly improved performance on memory-intensive tasks, such as graph processing and machine learning. By leveraging 3D-stacked DRAM memory on FPGAs, it is possible to realize the Near-Memory Computing (NMC) paradigm, which involves offloading some kernels to be processed close to the memory. While there have been many studies on NMC accelerators, there is no established method for determining which application kernels are suitable for execution near the HBM. To fully realize the potential of FPGA-HBM architectures, it is important to identify offloading candidates without relying on programmers' knowledge. However, this is a non-trivial task due to the complexity of modern applications. To address this issue, we propose a compiler-assisted tool-flow for the automatic selection of kernels to be offloaded.

The concept of near-memory computing (NMC) has emerged as a promising solution to address the memory wall challenges faced by future computing architectures. By utilizing modern systems that integrate 3D-stacked DRAM memory, the NMC paradigm minimizes unnecessary data movement between the memory subsystem and the CPU. FPGA vendors have incorporated 3D-stacked memories into their products to meet the increasing bandwidth requirements of memory-intensive applications, enabling FPGAs to compete with GPU solutions in terms of speed and energy efficiency. Recent NMC proposals focus on different data processing workloads, including graph processing and machine learning. This work addresses the research questions of how to leverage the full bandwidth of 3D-stacked high-bandwidth memory and how to facilitate the adoption of the near-memory computing paradigm.

Guest Editors Introduction: Special Issue on Network-on-Chip Architectures of the Future (NoCArc

The near-memory computing (NMC) paradigm has transpired as a promising method for overcoming the memory wall challenges of future computing architectures. Modern systems integrating 3D-stacked DRAM memory can be leveraged to prevent unnecessary data movement between the main memory and the CPU. FPGA vendors have started introducing 3D memories to their products in an effort to remain competitive on bandwidth requirements of modern memory-intensive applications. Recent NMC proposals target various types of data processing workloads such as graph processing, MapReduce, sorting, machine learning, and database analytics. In this article, we conduct a literature survey on previous proposals of NMC systems on FPGAs integrated with 3D memories. By leveraging the high bandwidth offered from such memories together with specifically designed hardware, FPGA architectures have become a competitor to GPU solutions in terms of speed and energy efficiency. Various FPGA-based NMC designs have been proposed with software and hardware optimization methods to achieve high performance and energy efficiency. Our review investigates various aspects of NMC designs such as platforms, architectures, workloads, and tools. We identify the key challenges and open issues with future research directions.

In recent times, Network-on-Chip (NoC) has become state of the art for communication in Multiprocessor System-on-Chip due to the existing scalability issues in this area. However, these systems are exposed to security threats such as extraction of secret information. Therefore, the need for secure communication arises in such environments. In this work, we present a communication protocol based on authenticated encryption with recovery mechanisms to establish secure end-to-end communication between the NoC nodes. In addition, a selected key agreement approach required for secure communication is implemented. The security functionality is located in the network adapter of each processing element. If data is tampered with or deleted during transmission, recovery mechanisms ensure that the corrupted data is retransmitted by the network adapter without the need of interference from the processing element. We simulated and implemented the complete system with SystemC TLM using the NoC simulation platform PANACA. Our results show that we can keep a high rate of correctly transmitted information even when attackers infiltrated the NoC system.

The amount of image data to be processed has increased tremendously over the last decades. One major computer vision task is the extraction of information to find patterns in and between images. One well-studied pattern recognition algorithm is AKAZE which builds a nonlinear scale space to detect features. While being more efficient compared to its predecessor KAZE, the computational demands of AKAZE are still high. Since many real-world computer vision applications require fast computations, sometimes under hard power and time constraints, FPGAs became a focus as a suitable target platform. This work presents a highly modularized and parameterizable implementation of the AKAZE feature detection algorithm integrated into HiFlipVX, which is a High-Level Synthesis library based on the OpenVX standard. The fine granular modularization and the generic design of the implemented functions allows them to be easily reused, increasing the workflow for other computer vision algorithms. The high degree of parameterization and extension of the library enables also a fast and extensive exploration of the design space. The proposed design achieved a high repeatability and frame rate of up to 480 frames per second for an image resolution of 1920×1080 compared to related work.

The ability of the reconfigurable systems to provide flexible and high-performance hardware has contributed to the fact that their popularity and multifaceted usage increased enormously in recent years [1] . They are occupying a central position in our modern complex systems. The development of Field Programmable Gate Arrays (FPGA) has taken hardware flexibility, in general, one step further. In recent years, many approaches have been developed that exploit dynamic reconfigurability of FPGAs, especially Xilinx FPGAs. Dynamic partial reconfiguration (DPR) and especially relocation are well-established and promising techniques in this area. In this context, the use of partial reconfiguration to add the adaptability feature to the design makes system design even more complex [2] . Therefore, solutions that help to reduce time and design efforts are needed. One of these solutions is bitstream manipulation. This approach leads to the user being able to perform modifications at runtime, thus reducing design time significantly.

FPGA virtualization allows the shared usage of an FPGA by several operating systems with different criticality levels. To avoid mutual interference, most state-of-the-art systems strictly isolate subsystems in spatial respect at the expense of lower resource utilization. We present an allocation and scheduling strategy for hardware tasks that improves resource utilization while respecting different real-time levels (hard, soft, and no real-time) of guest operating systems. To not jeopardize deadlines, Dynamic Partial Reconfiguration (DPR) latencies are reduced by reusing, prefetching and reserving of hardware accelerators. Compared with an existing scheduler for hardware tasks, we could increase the resource usage by 156% while deadline misses were reduced by 6%.

Systems with hardware that can dynamically and autonomously change their architecture and behavior by interacting with their environment are becoming very valuable in modern applications. Therefore, research and development in intrinsically evolvable embedded systems are becoming increasingly attractive. Runtime reconfiguration and relocation are a promising approach for designing self-adaptive and self-optimizing autonomous embedded systems. The vision behind this PhD work is to provide an all-encompassing framework to automate all the challenging tasks required for designing self-adaptive systems. This paper presents our framework and preliminary results and highlights our next steps and future work.

Multi/manycore Systems-on-Chip are increasingly adopted for heterogeneous systems, providing a high degree of computing scalability and energy efficiency. However, the steady increase in heterogeneous tiles number leads to an expansion in resource usage and design cost. Therefore, reusability and modularity of the tile architecture to support different types of compute or memory units are key elements to reduce resource usage. Meanwhile, with the proliferation of RISC-V instruction set architecture, the modularity and reusability of compute tiles have been increased. In this work, we present a modular and reusable memory/accelerator tile architecture that supports two modes of operations as a memory or an accelerator tile. The proposed tile architecture is suitable to be integrated into a NoC based manycore architecture along with RISC-V based compute tiles. The hybrid tile features a shared non-coherent scratchpad memory that can be accessed directly by RISC-V compute tiles through NoC or by the local hardware accelerator logic inside the tile. Tile mode configuration and data transfer over the NoC are managed through control messages issued by RISC-V compute tiles based on running application requirements. Moreover, the proposed tile supports the flexibility to change the local hardware accelerator functionality at run-time using dynamic and partial reconfiguration. For evaluation, two manycore configurations are developed including 4 and 8 RISC-V compute tiles with 4 cores per tile. Several use cases based on signal processing kernels and hardware accelerators are used for performance evaluation in terms of memory transfer latency and computing time for two manycore configurations. Maximum data transfer throughput of 500 MB/s is achieved between the proposed hybrid tile and a single RISC-V compute tile. The proposed tile architecture is implemented and evaluated on a Xilinx Virtex Ultrascale+ FPGA.

Robotic systems compute data from multiple sensors to perform several actions (e.g., path planning, object detection). FPGA - based architectures for such systems may consist of several accelerators to process compute-intensive algorithms. Designing and implementing such complex systems tends to be an arduous task. This work proposes a modeling approach to generate architectures for such applications, compliant with existing robotics middlewares (e.g., ROS, ROS2). The challenge is to have a compact, yet expressive description of the system with just enough information to generate all required components and to integrate existing algorithms. This system model must be generalizable, so it is not application-dependent, and it must exploit the benefits of FPGAs over software solutions. Previous work mainly focused on individual accelerators rather than all components involved in a system and their interactions. The proposed approach exploits the advantages of model-driven engineering and model-based code generation to produce all components, i.e., message converters acting as middleware interfaces and wrappers to integrate algorithms. Data type and data flow analysis are performed to derive the necessary information to generate the components and their connections. Solutions to several identified challenges for generating entire systems from such models are evaluated using four different use cases.

The increasing complexity of reconfigurable embedded systems often requires the integration of multiple applications with potentially different levels of criticality on the same hardware platform. As the deployment scales, there is a need for resource management, isolation, and performance that makes FPGA virtualization techniques a key consideration. FPGA virtualization enables multiple guest operating systems to run with different requirements, such as real-time, safety, or security. Most state-of-the-art systems incorporate mechanisms to strictly isolate subsystems in spatial respect at the expense of lower resource utilization. In this work, we present L4ReC, a microkernel-based virtualization layer that enables the sharing of reconfigurable resources among multiple virtual machines. The mapping and scheduling strategy for hardware threads considers not only deadlines, but also the real-time levels of guest operating systems. A POSIX thread-based interface facilitates the access to hardware accelerators. Compared with an existing scheduler for hardware threads, the average utilization factor - indicating the FPGA resource usage - is 1,9 times higher when threads are mapped and scheduled with L4ReC. Deadline misses are reduced by 3%.

With the trend to consolidate multiple systems onto the same hardware platform, which can be observed for example in the automotive industry, virtualization of embedded systems becomes increasingly important. Often small and efficient real time operating systems (RTOS) run besides general purpose operating systems (GPOS) with a convenient, high level application interface. When virtualizing embedded reconfigurable systems, FPGA characteristics have to be considered like limited FPGA area and high reconfiguration latencies. We present the FPGA virtualization layer L4ReC that enables the shared usage of reconfigurable resources by several guest operating systems under consideration of the constraints given by embedded reconfigurable systems. First results target isolation, energy efficiency, and FPGA resource management considering special requirements of guest operating systems.

Machine learning algorithms are becoming more complicated with time in order to solve complex problems. This is creating a gap for embedded system solutions e.g. General-Purpose Processors (GPPs), Graphic Processing Units (GPUs), and hardware accelerators, for the machine learning algorithms. To bridge the gap between the available solutions, Application Specific Instruction-set Processors (ASIPs) are a promising solution. ASIPs are processor designs with a tailored architecture for a specific application. This allows a better efficiency (performance-to-power) ratio for the application ex-ecution. Furthermore, it adds more flexibility to the system as compared with hardware accelerators. The scope of this Ph. D. work is to develop a RISC-V-based ASIP for machine learning applications and explore the design space of the optimizations. RISC-V is an open-source Instruction-Set-Architecture (ISA) and allows the addition of custom application-specific instructions to the ISA. In the scope of this work three main design space optimization of ASIPs will be explored; specialized application-specific ISA, vector processing (for data-level parallelism), and multi-core architecture (for task-level parallelism). RISC- V 32-bit architecture is used as the base platform. For vector processing, RISC- V V-extension is utilized for a SIMD-based architecture called Vector Processing Unit (VPU) which is coupled with a 32-bit RISC- V host CPU. A modular memory system is implemented to have a shared (bus-based) and distributed (NoC- based) multi-core system. The memory system increases the flexibility and scalability of the system. Other known machine learning platforms are also explored and used as a comparison case.

Coarse-Grained Reconfigurable Architectures (CGRAs) are promising solutions to achieve more performance with the end of Moore's law. Thanks to word-level programmability, they are more energy-efficient compared to FPGAs. Although ASICs can minimize energy, they suffer from high Non-Recurring Engineering (NRE) costs and inflexibility. CGRAs provide near ASIC energy efficiency and are deployed in the literature to accelerate low-power and high-performance applications. However, focusing on low-power CGRAs is crucial as a high volume of data should be processed on a resource-constrained device by the development of IoT and Machine Learning applications. This survey has reviewed and categorized CGRA architectures from processing elements, interconnect networks, and memory points of view and derived guidelines for energy-efficient CGRA design.

Computing heterogeneity is a crucial demand for today's systems-on-chip requirements. Current many-core computing architectures feature a scalable number of heterogeneous compute units supporting a wide range of application domains. However, supporting both heterogeneity and computing scalability brings significant design challenges related to on-chip communication between heterogeneous components and run-time management. This leads to growing design time, development cost, and lack of hardware modularity and re-usability. This PhD work aims to develop and design a modular and adaptive hardware platform for realizing different types and taxonomies of heterogeneous many-core systems targeting FPGAs reusing the same hardware components. The proposed platform is based on a modular and scalable tile-based architecture supporting heterogeneous instruction set architectures (ISAs), seamless integration of custom hardware accelerators and several memory hierarchies. In this paper, the proposed tile-based platform, preliminary results, and evaluation are presented targeting FPGAs. Finally, planned and future works are highlighted.

There have been partial contributions in the state-of-the-art about FPGAs being part of robotics systems. However, a study of FPGAs as a whole for robotics systems is missing in the literature. This means that defining all the components required for an FPGA-based system for robotics applications as a whole, their integration into existing solutions, and the generation of said components has not been done. The traditional robotics workflow involves many disciplines (e.g., mechatronics, control, software) where experts deal with the integration of all individual parts. We propose a model-based component-oriented workflow, focusing on easing the integration of all the parts to deploy FPGA-based robotics systems automatically. Our systematic approach reduces ten times the effort needed to deploy a system than doing it manually. Furthermore, it converts an arduous and error-prone process of doing it manually into a simple system description.

This article introduces GraphCL, an automated system for seamlessly mapping multi-kernel applications to multiple computing devices. GraphCL consists of a C ++ API and a runtime that abstracts and simplifies the execution of multi-kernel applications on heterogeneous platforms across multiple devices. The GraphCL approach has three steps. First, the application designer provides a kernel graph. In the second phase, GraphCL computes the execution schedule. After the schedule has been computed, the runtime uses the execution schedule to enqueue in parallel the processing for all system processors. GraphCL takes the kernel dependencies and the processor performance differences into account during the schedule calculation process. By deciding on the schedule, GraphCL transparently manages the order of execution and data transfers for each processor. On two asymmetric workstations, GraphCL achieves an average acceleration of 1.8x compared to the fastest device. GraphCL achieves also for the set of multi-kernel benchmarks an average 24.5% energy reduction compared to the lazy partition heuristic, that uses all the system processors without considering their power usage.

FPGAs are an excellent platform to implement computer vision applications, since these applications tend to offer a high level of parallelism with many data-independent operations. However, the freedom in the solution design space of FPGAs represents a problem because each solution must be individually designed, verified, and tuned. The emergence of High Level Synthesis (HLS) helps solving this problem and has allowed the implementation of open programming standards as OpenVX for computer vision applications on FPGAs, such as the HiFlipVX library developed exclusively for Xilinx devices. Although with the HiFlipVX library, designers can develop solutions efficiently on Xilinx, they do not have an approach to port and run their code on FPGAs from other manufacturers. This work extends the HiFlipVX capabilities in two significant ways: supporting Intel FPGA devices and enabling execution on discrete FPGA accelerators. To provide both without affecting user-facing code, the new carried out implementation combines two HLS programming models: C++, using Intel’s system of tasks, and OpenCL, which provides the CPU interoperability. Comparing with pure OpenCL implementations, this work reduces kernel dispatch resources, saving up to 24% of ALUT resources for each kernel in a graph, and improves performance 2.6 × and energy consumption 1.6 × on average for a set of representative applications, compared with state-of-the-art frameworks.

The computational intensity in embedded processing applications is increasing. This requires domain-specific embedded platforms in order to achieve maximum performance per watt of the system. With the arrival of open-source instruction set architectures such as RISC-V, and different domain-specific architecture development toolchains, the trend of application-specific architectures is increasing. In this paper, a parameterizable Vector Processing Unit (VPU) is presented based on a subset of V-extension from the RISC-V instruction set architecture (ISA) for embedded processing. Two key configurable parameters for the proposed VPU are vector length (VLEN) and the number of execution lanes. These parameters allow design space exploration for the VPU for different configurations and help to understand which application scenarios would fit for certain configurations. The proposed VPU was integrated into a 32-bit RISC-V processor. For maximum parallelization configuration, 2.3 x fewer cycles per instructions were achieved as compared to a RISC-V processor. Moreover, a relative cycle gain of 33-73% was achieved for different configurations as compared with the RISC-V processor.

The near-data processing (NDP) paradigm has emerged as a promising solution for the memory wall challenges of future computing architectures. Modern 3D-stacked DRAM systems can be exploited to prevent unnecessary data movement between the main memory and the CPU. To date, no standardized simulation frameworks or benchmarks are available for the systematic evaluation of NDP systems. Identifying which type of high-performance 3D memory is suitable to use in an NDP system remains a challenge. This is mainly due to the fact that understanding the interactions between modern workloads and the memory subsystem is not a trivial task. Each memory type has its advantages and drawbacks. Additionally, memory access patterns vary greatly across applications. As a result, the performance of a given application on a given memory type is difficult to intuitively predict. There is no specific memory type that can effectively provide high performance for all applications.In this work, we propose a machine learning framework that can efficiently decide which NDP system is suitable for an application. The framework relies on performance prediction based on an input set of application characteristics. For each NDP system we are examining, we build a machine learning model that can accurately predict performance of previously unseen applications on this system. Our models are on average 200x faster than architectural simulation. They can accurately predict performance with coefficients of determination ranging between 0.88 and 0.92, and root mean square errors ranging between 0.08 and 0.19.

Nowadays, drones can be seen in various applications in industry like surveillance and transportation. Industrial drones leverage fully-fledged computer vision techniques, such as object detection based on Deep Learning Neural Networks (DNN), to efficiently perform these objectives. Those techniques come with a high computational effort and are implemented on distributed schemes using ground devices with high performance and power consumption. This limits a drone's operational range since it has to communicate with the ground devices constantly. To alleviate such constraints, an optimized, low-power perception system on the drone is desirable. This work improves a trained DNN architecture to navigate a UAV introduced by the University of Zurich called DroNet. DroNet is computationally expensive and has a high power consumption, making it unsuitable for embedded platforms because of low memory and computational power. In this paper, a ROS-based architecture is first designed to port DroNet on a low-power Jetson Nano board, which conducts the drone's perception and control tasks. Secondly, tuning parameters and various schemes have been carried out to run the inference of the DNN efficiently. To implement the different layers in DNNs, Nvidia's TensorRT SDK is used to compile a high-performance inference engine for the Jetson Nano. Results showed that the Jetson Nano can achieve real-time performance, with 47 frames per second using a Winograd convolution and well-tuned parallelization parameters. The implementation can also achieve a speedup of 2× as compared with the Jetson Nanos ARM CPU while increasing the power consumption by 54%. Finally, the Jetson Nano's usability for drone inference algorithm is shown, achieving real-time response using the DroNet DNN without losing detection accuracy.

A major concern with battery-operated devices is power-awareness and its appropriate computing. The power dissipation of such systems is usually considered a hardware problem. However, it can be solved by implementing power-aware techniques. Such algorithms have shown promise as an approach to dynamically adjust the power consumption of embedded systems within feasible ranges. One of the most popular power-saving techniques is Dynamic Voltage and Frequency Scaling (DVFS). Besides the power management, an accurate and fast power monitoring service is necessary on embedded platforms to reduce power consumption. In this paper, we provide an overview of power-aware computing platforms based on different application domains. It intends to summarize recently published research results related to power-aware computing architectures using Field Programmable Gate Arrays (FPGAs). We identify trends and highlight key future directions for power management techniques and power monitoring services.

Real-time Operating Systems (RTOSs) are mainly implemented in software and sequentially executed on processors. The periodic call of the task scheduling service introduces additional overhead in software and eventually leads to jitter. However, the occurring overhead can be shortened or eliminated by using reconfigurable systems. Besides, dynamically adjusting power dissipation of reconfigurable systems leads to a change in the execution time of applications, so deadlines may not be met. Therefore, careful study of the impact of such optimizations on real-time capabilities is needed. The presented PhD project deals with offloading of RTOS components considering power dissipation on reconfigurable platforms. For this purpose, the task scheduling of FreeRTOS has already been offloaded to a co-processor while scaling voltage and frequency on XC7Z020. This reduced the execution time of the task scheduling by 38.9%.

Motivated by an increasing interest from startups in embedded Artificial Intelligence (AI) and by their limited expertise, the AITIA Project targets the development of embedded AI techniques for industrial applications. This extended abstract presents the motivation and the solutions being developed towards four use cases: smart sensors, network intrusion detection, driver-assistance systems, and Industry 4.0.

Reconfigurable many-core computing platforms are gaining increasing attention for cloud and edge computing because of their high degree of scalability as well as flexibility. Heterogeneous many-core architectures provide more computing capabilities for domain-specific and general-purpose applications. However, bringing heterogeneous and custom computing elements together increases on-chip communication and run-time management complexities. This leads to growing design time and development cost, in addition to lack of platform re-usability. The scope of this PhD work is the design of a modifiable and modular hardware platform that provides a high degree of agility to change types or specifications of computing elements at design and run-time to achieve the best performance for different application demands using the same platform components. Different acceleration strategies and memory hierarchies are supported. In this paper, the proposed platform, preliminary results, and evaluation are presented targeting FPGAs. Finally, planned and future works are highlighted.

Modern robotic platforms are increasingly complex due to incorporating various heterogeneous sensors and several actuators generating data at large frequencies. They are mostly based on embedded computers but relying on software solutions not entirely suited for parallel processing. FPGAs are an ideal candidate to solve this issue, enhancing those systems’ computing capabilities while still being programmable. We follow a holistic approach and study which components are needed for FPGA-based robotic applications. We propose a model-based component-oriented workflow to realize such applications. Its only input is a System’s Specification to generate components to manage N accelerators, their behavior and interfaces to several middlewares. Only simple modifications to specifications rather than complex changes to implementations are needed to generate all these tailored components for any kind of robotic applications.

Nowadays, the increasing number of processing elements (PEs) in Multiprocessor Systems-on-Chip (MPSoCs) requires a scalable on-chip interconnect. Networks-on-Chip (NoCs) have emerged as the most promising communication technology for MPSoCs. Novel routers that reduce the communication overhead by integrating a processing layer into the communication layer of MPSoCs and the corresponding flow control of packets defined as Wormhole Computing are presented. The routers are constructed with processing units inside the input buffers providing application-specific operations that can be executed on transferred data. Hence, the communication time can be efficiently used by processing data that is sent by packets through the NoC. A KPN-based computation model has been modified to support not only the mapping of tasks to PEs but also the mapping to routers. In addition to analytical considerations, the novel routers have been evaluated with signal processing applications on a Xilinx Zynq SoC. The analytical considerations prove that a speedup can be achieved by moving a sequence of instructions from processors to routers. The results of both use cases show better exploitation of the communication time by up to 42.8% and a speedup of up to 5x for a single task.

The increase of size, capabilities, and speed of FPGAs enables the shared usage of reconfigurable resources by multiple applications and even operating systems. While research on FPGA virtualization in HPC-datacenters and cloud is already well advanced, it is a rather new concept for embedded systems. The necessity for FPGA virtualization of embedded systems results from the trend to integrate multiple environments into the same hardware platform. As multiple guest operating systems with different requirements, e.g., regarding real-time, security, safety, or reliability share the same resources, the focus of research lies on isolation under the constraint of having minimal impact on the overall system. Drivers for this development are, e.g., computation intensive AI-based applications in the automotive or medical field, embedded 5G edge computing systems, or the consolidation of electronic control units (ECUs) on a centralized MPSoC with the goal to increase reliability by reducing complexity. This survey outlines key concepts of hypervisor-based virtualization of embedded reconfigurable systems. Hypervisor approaches are compared and classified into FPGA-based hypervisors, MPSoC-based hypervisors and hypervisors for distributed embedded reconfigurable systems. Strong points and limitations are pointed out and future trends for virtualization of embedded reconfigurable systems are identified.

In this work, we present a solution to a common problem encountered when using FPGAs in dynamic, ever-changing environments. Even when using dynamic function exchange to accommodate changing workloads, partial bitstreams are typically not relocatable. So the runtime environment needs to store all reconfigurable partition/reconfigurable module combinations as separate bitstreams. We present a modular and highly flexible tool (AMAH-Flex) that converts any static and reconfigurable system into a 2 dimensional dynamically relocatable system. It also features a fully automated floorplanning phase, closing the automation gap between synthesis and bitstream relocation. It integrates with the Xilinx Vivado toolchain and supports both FPGA architectures, the 7-Series and the UltraScale+. In addition, AMAH-Flex can be ported to any Xilinx FPGA family, starting with the 7-Series. We demonstrate the functionality of our tool in several reconfiguration scenarios on four different FPGA families and show that AMAH-Flex saves up to 80% of partial bitstreams.

In Computer Vision, open programming standards such as OpenVX have emerged to bring together portability and acceleration across devices. Unfortunately, achieving both goals on FPGAs remains a challenge because FPGAs still require to adapt the code with proprietary extensions. Exclusively for Xilinx devices, the HiFlipVX open source library partially solves this problem by offering a clean C++ OpenVX API that offers the performance of proprietary extensions without exposing its complexity to programmer. While HiFlipVX enables portability within Xilinx devices, portability between FPGA manufacturers remains an open challenge. This work extends the HiFlipVX's capabilities with a twofold goal: i) to support Intel FPGA devices with different memory configurations, and ii) to enable execution on FPGAs as discrete accelerators. To accomplish these goals, the proposed implementation combines two HLS programming models: C++, using Intel's system of tasks that enables to coalesce nodes and reduce control overhead, and OpenCL, which provides efficient compute kernel nodes. On Intel FPGAs, compared with pure OpenCL implementations, the proposed implementation reduces kernel dispatch resources, saving up to 24% of ALUT resources for each kernel in a graph, and improves performance. Gains are 2.6× on average for representative applications, such as Canny edge detector, or Census transform, compared with state-of-the-art frameworks.

In this work, we present CoopCL, an C++ API and runtime that abstracts and unifies the cooperative workload execution on multi-core CPU and GPU. The CoopCL takes a OpenCL-C kernel function and automatically uses both the CPU and the GPU to execute it in parallel. We propose a method that transparently manages the data transfers and synchronization necessary to ensure a coherence without requiring any effort from the programmer. The CoopCL is completely portable across different machines including platforms with discrete and integrated GPUs. Across a set of diverse benchmarks, our runtime shows a mean speedup of nearly 10% over a GPU only execution and 30% over a multi-core CPU. We also achieve up to a 52% reduction in energy consumption compared to the CPU only execution.

Networks-on-chip (NoCs) acquired substantial advancements as the typical solution for a modular, flexible and high performance communication infrastructure coping with the scalable Multi-/Manycores technology. However, the increasing chip complexity heading towards thousand cores, together with the approaching dark-silicon era, puts energy efficiency as an integral design key for future NoC-based multicores, where NoCs are significantly contributing to the total chip power. In this paper, we propose HPPT-NoC, a dark-silicon inspired energy-efficient hierarchical TDM NoC with online distributed setup-scheme. The proposed network makes use of the dim silicon parts of the chip to hierarchically connect quad-routers units. Normal routers operate at full-chip-frequency at high supply level, and hierarchical routers operate at half-chip-frequency and lower supply voltage with adequate synchronization. Routers follow a proposed TDM architecture that separates the datapath from the control-setup planes. This allows separate clocking and operating supplies between data and control and to keep the control-setup as a single-slot-cycle design independent of the datapath slot size. The proposed NoC architecture is evaluated versus a base NoC from the state-of-the-art in terms of performance and hardware results using Synopsys VCS and Synopsys Design Compiler for SAED90nm and SAED32nm technologies. The obtained results highlight the power-frequency-trading feature supported by the proposed hierarchical NoC through the configurable data-control clock relation and maintained over the different technology nodes. With the same power budget of the base NoC, the proposed architecture provides up to 74% setup latency enhancement, 32% increased NoC saturation load, and 21% higher success rates, offering up to 78% improved power delay product. On the other hand, with 38% power savings, the proposed NoC provides up to 37% enhanced latency and 15% higher success rates, with 72% enhanced power delay product. The proposed design consumes almost double the area of the base NoC, however with an average of 56% under-clocked (dim) silicon area operating at half to quarter the maximum chip frequency. This results in reduced power density as a main concern in the dark-silicon era down to 24% of the base NoC.

The field of computer vision is continuously increasing and becoming more complex and power demanding. Using feature detection and description allows a fast object detection without needing big databases. FPGAs are predestined for different requirements, like real-time and power constraints, which are important in many application areas. This work proposes a new pattern recognition algorithm, based on an improved Accelerated KAZE (AKAZE) detector and Fast Retina Keypoint (FREAK) descriptor. Our software implementation increased the repeatability in comparison to the original algorithm using optimized configurations. The percentage of correct matching features between two images (repeatability) increased from 85.7% to 91.4%, while the computation time decreases from 70.3ms to 24.9ms. Furthermore, we present an efficient FPGA implementation of the FREAK descriptor. The accelerator processes 2048 features at 73.4 frames per second; achieving a repeatability of 90.9%, while being optimized for resource utilization and memory bandwidth consumption. Additionally, we show an efficient Integral Image implementation that processes four image pixels per clock cycle at a high frequency (204 MHz on xc7z020clg484-1) consuming minimum resources.

This article presents Whisper, a fast and reliable protocol to flood small amounts of data into a multi-hop network. Whisper makes use of synchronous transmissions, a technique first introduced by the Glossy flooding protocol. In contrast to Glossy, Whisper does not let the radio switch from receive to transmit mode between messages. Instead, it makes nodes continuously transmit identical copies of the message and eliminates the gaps between subsequent transmissions. To this end, Whisper embeds the message to be flooded into a signaling packet that is composed of multiple packlets —where a packlet is a portion of the message payload that mimics the structure of an actual packet. A node must intercept only one of the packlets to detect that there is an ongoing transmission and that it should start forwarding the message. This allows Whisper to speed up the propagation of the flood and, thus, to reduce the overall radio-on time of the nodes. Our evaluation on the FlockLab testbed shows that Whisper achieves comparable reliability but 2× lower radio-on time than Glossy. We further show that by embedding Whisper in an existing data collection application, we can more than double the lifetime of the network.

This research work presents an intrusive methodology for debugging of embedded designs by using artificial intelligence technique. In this methodology, a cycle-accurate lossless debugging system with unlimited trace window can be used for debugging. Visibility of the embedded hardware is enhanced by an access network which also eliminates the need for frequent re-synthesis due to change in signal set. The controlling processor can configure the required network through software. A connectivity tool is developed which permits error-free connection of the DUT with the debugging system by using IP-XACT files. A correspondence analysis between the debugging results of the implemented hardware and its simulation results can be performed to speed up the debugging process. The debugging system can be partially reconfigured to any embedded design at runtime which can not only reduce the time spent on iterative place and route process of traditional debugging solutions but also makes the FPGA resources available to the user when debugging is not required

Current cache Side-Channel Attacks (SCAs) countermeasures have not been designed for many-core architectures and need to be revisited in order to be practical for these new technologies. Spatial isolation of resources for sensitive applications has been proposed taking advantage of the large number of resources offered by these architectures. This solution avoids cache sharing with sensitive processes. Consequently, their cache activity cannot be monitored and cache SCAs cannot be performed. This work focuses on the implementation of this technique in order to minimize the induced performance overhead. Different strategies for the management of isolated secure zones are implemented and compared.

Due to energy efficiency, heterogeneous computing is gaining more and more attention. Since FPGA implementations are time consuming, high-level synthesis (HLS) is used to close the productivity gap. OpenCL has become accepted as a good programming model for HLS, due to its portability, good capability of design verification and rich instruction set. This work implements different optimization strategies using OpenCL for a heterogeneous system containing CPU, integrated GPU, GPU and FPGA. Energy efficiency and performance of the architectures are compared using a feature detection algorithm. It is shown how to maximize performance while hitting the maximum memory bandwidth and keeping the resource utilization low for the SDAccel tool from Xilinx. The evaluation shows the great streaming capability of OpenCL for FPGAs. The FPGA achieves a speed up of 62.8 and consumes 49 times less energy for the application in comparison to an optimized single threaded CPU implementation in full HD.

Multi-Processor Systems-on-Chip (MPSoCs) have emerged as an evolution trend to meet the growing complexity of embedded applications with increasing computation parallelism. Particularly, real-time applications make out a significant portion of the embedded field. Networks-on-Chip (NoCs) are the backbone of communications in an MPSoC platform. However, the use of NoCs in real-time systems imposes complex constraints on the overall design. This paper discusses the challenges faced, when designing NoCs for real-time applications. Contributions in this area are surveyed on the level of guaranteed Quality-of-Service (QoS) support, adaptivity, and energy efficient techniques. Furthermore, the evaluation methodologies and experimental performance measurements of real-time NoCs are examined. This survey provides a comprehensive overview of existing endeavors in real-time NoCs and gives an insight towards future promising research points in this field.

Due to the demographic change in western society, new challenges regarding healthcare of the elderly population are at the verge of surfacing. Since young people are not capable of sustaining an adequate healthcare for elderly people, new healthcare fields have to be devised. Recent advances in information and communication technology enable the support of elderly people in their domestic environment. The EU project RADIO will design of an old age compliant smart home environment which specializes in fulfilling the needs of elderly people. This is partially achieved through a mobile robot platform which serves as an assistant to the respective elderly person. Apart from this, the robot also functions as a mobile sensor platform. Under this context, unobtrusiveness is of paramount importance since the robot should be a natural participant of patients' daily life. This paper discusses such a healthcare facility, analyses its requirements and poses the challenges towards this direction.

No abstract available.

Today ubiquitous computing is steadily growing in daily life, leading to an increasing need of resource awareness especially for devices with limited energy source. The running applications may differ significantly in their requirements and priority and these variations can occur during a single running application as well. Apart from the applications' constraints, there are regularly restrictions regarding the power source, which can vary during runtime. To tackle these issues, the design should focus on systems that can dynamically optimize themselves, according to the current requirements. Adaptive processors offer great advantages, such as the possibility to reconfigure the microarchitecture to specific needs online. Thus, it is possible for the system to be optimized for each stage of the executing applications and the environmental conditions. The design space of adaptive systems is vast if many parameters can be adjusted during runtime. In order to develop and operate these systems, several different approaches must be taken into account. In this work, new design concepts are presented, together with a discussion of future trends in the field of adaptive processing systems.

No abstract available.

Reliability in embedded systems is crucial for many application domains. Especially, for safety critical application, as they can be found in the automotive and avionic domain, a high reliability has to be ensured. The technology in chip production undergoes a steady shrinking process from nowadays 25 nanometers. It is proven that coming technologies, which are much smaller, can have a higher defect rate after production, but also at runtime. The physical effects at runtime come from a higher susceptibility for radiation. Since the silicon die of a field programmable gate array (FPGA) includes a high amount of physical wiring, the radiation effect plays here a major role. Therefore, this article describes an approach of a reliable Network-on-Chip (NoC) which can be used for an FPGA-based system. The article describes the concept and the physical realization of this NoC and evaluates its reliability.

No abstract available.

Efficiently managing the parallel execution of various application tasks onto a heterogeneous multi-core system consisting of a combination of processors and accelerators is a difficult task due to the complex system architecture. The management of reconfigurable multi-core systems which exploit dynamic and partial reconfiguration in order to, e.g. increase the number of processing elements to fulfill the performance demands of the application, is even more complicated. This paper presents a special virtualization layer consisting of one central server and several distributed computing clients to virtualize the complex and adaptive heterogeneous multi-core architecture and to autonomously manage the distribution of the parallel computation tasks onto the different processing elements.

The mapping process of high performance embedded applications to today's multiprocessor system on chip devices suffers from a complex tool chain and programming process. The problem here is the expression of parallelism with a pure imperative programming language which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from different domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction. This holistic solution of the toolchain allows the complexity of both the application and the architecture to be hidden, which leads to a better acceptance, reduced development cost, and shorter time-to-market. Driven by the technology restrictions in chip design, the end of exponential growth of clock speeds, and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies.

Virtualizing complex hardware, such as heterogeneous multiprocessor systems, enables developers to use standard Application Programming Interfaces (APIs) for application integration. Especially, the supply of an Operating System (OS) is well appreciated since many features such as drivers, the runtime environment and scheduling mechanisms are available and well established. For this purpose, Embedded Linux was used as basis OS and extended in order to be able to manage a Runtime Adaptive Multi-Processor System-on-Chip (RAMPSoC) and to provide the standard Message Passing Interface (MPI). This paper describes the adaptation of the Linux kernel supporting MPI with runtime libraries as well as the integration of the software/hardware drivers which supply the message transfer over a reconfigurable and heterogeneous Network-on-Chip (NoC).

Until today, the efficient partitioning and mapping of applications for multiprocessor systems is a challenging task. The deployment of reconfigurable hardware in this domain helps to meet the application requirements more efficiently due to hardware adaptation at design and runtime, which is not applicable in the traditional multiprocessor domain. To exploit this novel degree of freedom in multiprocessor system-on-chip (MPSoC) technology, a novel design methodology is needed, which helps to hide the complexity of the hardware architecture and its realization alternatives from the developer. This paper shows one approach for such a design methodology for the development of the hardware architecture and the application partitioning and mapping. A novel multistep approach based on hierarchical clustering is used for partitioning of the software application and for configuration of a runtime adaptive multiprocessor system. Furthermore, each application module is then partitioned in a Hardware-Software Codesign process in order to achieve a maximum of performance on the local processors and therefore in general for the MPSoC.

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Multiprocessor System-on-Chip is a promising realization alternative for the next generation of computing architectures providing the required data processing performance in high performance computing applications. Numerous scientists from industry and academic institutions investigate and develop novel processing elements and accelerators as can be seen in real devices like IBM's Cell or nVIDIA's Tesla GPU. Nevertheless, the on-chip communication of these multiple processor elements has to be optimized tailored to the actual requirement of the data to be processed. Network-on-Chip (NoC), Bus-based or even heterogeneous communication on chip often suffer from the fact of being inflexible due to their fixed physical realization. This paper presents a novel approach for a NoC, exploiting circuit-and packed-switched communication as well as a run-time adaptive and heterogeneous topology. An application scenario from image processing exploiting the implemented NoC on an FPGA delivers results like performance data and hardware costs.

Multiprocessor hardware architectures enable to distribute tasks of an application to several microprocessors, in order to exploit parallelism for accelerating the performance of computation. Especially for the application domain of image data processing, where computation performance is a crucial factor to keep the real-time requirements, this approach is a promising solution for the assembly of high sophisticated algorithms e.g. for object tracking. Changing requirements and the necessary implementation of the tasks in terms of modified algorithms, precision and communication needs to be handled by software and hardware adaptation in state of the art architectures. Field programmable gate arrays (FPGAs) enable to exploit the adaptation of hardware cores and the software running on embedded microprocessor cores on an integrated multiprocessor system.

Current trends in high performance computing show, that the usage of multiprocessor systems on chip are one approach for the requirements of computing intensive applications. The multiprocessor system on chip (MPSoC) approaches often provide a static and homogeneous infrastructure of networked microprocessor on the chip die. A novel idea in this research area is to introduce the dynamic adaptivity of reconfigurable hardware in order to provide a flexible heterogeneous set of processing elements during run-time. This extension of the MPSoC idea by introducing run-time reconfiguration delivers a new degree of freedom for system design as well as for the optimized distribution of computing tasks to the adapted processing cells on the architecture related to the changing application requirements. The "computing in time and space"paradigm and the extension with the new degree of freedom for MPSoCs will be presented with the RAMPSoC approach described in this paper.

Since the 1990s reusable functional blocks, well known as IP-Cores, were integrated on one silicon die. These systems-on-chip (SoC) used a bus-based system for intermodule communication. Technology and flexibility issues forced to introduce a novel communication system called network-on-chip (NoC). Around 1999 this method was introduced and until then it is investigated by several research groups with the aim to connect different IP-Blocks through an effective, flexible and scalable communication network. Exploiting the flexibility of FPGAs, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic and partial reconfiguration. This paper presents an approach for exploiting dynamic and partial reconfiguration with Xilinx Virtex-II FPGAs for a multi-layer network-on-chip and the related techniques for adapting the network while run-time to the requirements of an application.

Modern generations of field-programmable gate arrays (FPGAs) allow for partial reconfiguration. In an online context, where the sequence of modules to be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of modules leads to progressive fragmentation of the available space, making defragmentation an important issue. We address this problem by proposing an online and an offline component for the defragmentation of the available space. We consider defragmenting the module layout on a reconfigurable device. This corresponds to solving a 2D strip packing problem. Problems of this type are NP-hard in the strong sense, and previous algorithmic results are rather limited. Based on a graph-theoretic characterization of feasible packings, we develop a method that can solve 2D defragmentation instances of practical size to optimality. Our approach is validated for a set of benchmark instances. We also discuss a simple strategy for dealing with online scenarios, called ldquoleast-interference fitrdquo (LIF); we give a number of analytic results that allow a comparison of LIF with the best offline solution, and demonstrate that it works well on benchmark instances of moderate size.