Packet classification has become increasingly complex and important to network equipment intended for future use. A recent trend to achieve complex packet classification is to use software-based methods, which tend to be slower than hardware-based methods. For search, this typically means using ternary content-addressable memory (TCAM) to make classification feasible. However, TCAM is not well-suited to the long (in bits) and sparse rules used for running advanced applications that require complicated classification. We propose a multi-dimension search engine (MDSE) that is optimized for use with long, sparse rules, and we propose a multi-dimensional TCAM scheme, which is an MDSE constructed to operate on TCAM. Through fine-grained simulations with real traffic, we show that our proposed search engine can reduce the power consumed by network equipment by about 85%.

Recently, energy consumption of routers has become a serious problem, hence power reduction is an urgent and important challenge. Existing routers always work 100% of their potentials regardless of required performance, such as volume of input traffic. However, semiconductor devices such as lookup logics, buffers, fabrics are not always fully utilized. In particular, the occupancy of packet buffer is very low in many cases, especially in core routers, which leads to unnecessary consumption of electric power. To solve this problem, a new buffer architecture called Sliced Packet Buffer was proposed. Dividing a whole buffer into multiple sub buffers (called slices) at the LSI level enables to control power management independently according to its occupancy. However, input traffic rate is another parameter for further power savings, which was not considered so far. In this paper, we propose a Two Dimensional Sliced Packet Buffer which enables power management according to not only the buffer occupancy but also the traffic volume. We also propose a model of accurate performance evaluation on energy consumption in the granularity of operational instruction. Through trace-driven simulations with real traffic, we show that our proposed packet buffer can reduce an average 66% of power consumption when an average input rate is 30%.

A two-level microprogrammed multiprocessor system, MUNAP, along with its support software has been developed as a research vehicle for solving nonnumeric and associated problems. The MUNAP system provides highly parallel and distributed functions for nonnumeric processing, such as variable length word addressing, data permutation at the microprogram level, and bit operation and field handling at the multinanoprogram level. To control these functions efficiently, a 28-bit microinstruction simultaneously drives several nanoprogram streams of 40-bit nanoinstructions in the four 16-bit processor units. This scheme not only provides the ability to organize a number of modular processing elements into a single, parallel processable computer system, but also allows MUNAP to change its architecture at the firmware level.