The Automatic Identification System (AIS) is a vessel tracking protocol used by the vast majority of the global maritime community. While AIS is a fantastic tool for preventing vessel collisions, it unfortunately has no built-in security. This project first provides a security vulnerability analysis of the current AIS system. We then propose the outline for a new protocol that addresses these vulnerabilities. This protocol maintains the anti-collision capabilities that AIS was designed to provide, but uses secured communications similar to those proposed in IEEE 1609 combined with a multi-tiered user-level approach to provide greater security. Finally, our proposed protocol is simulated from two perspectives: that of an average user as well as from a network perspective level. In aggregate, the results from these simulations suggest that our protocol keeps the existing usability of AIS while reducing potential security concerns.

Over the last seven years we have seen an exponential increase in the number of Bioinformatics databases available. These databases are becoming increasingly specialised and are often only known by a small community of users. This paper describes the implementation of a novel meta-database. Rather than simply displaying a list of databases that are available this project has used graphical data in the form of a family tree to show how the databases are related to one another. A general level of relatedness is described using fuzzy sets, this relationship compares every database against all the other databases to see how related they are. It facilitates an automatic construction of the tree when new databases are added.

Parallel machines have the potential to satisfy the large computational demands of real-time applications. These applications require a predictable communication network, where time-constrained traffic requires bounds on throughput and latency, while good average performance suffices for best-effort packets. This paper presents a new router architecture that tailors low-level routing, switching, arbitration, flow-control, and deadlock-avoidance policies to the conflicting demands of each traffic class. The router implements bandwidth regulation and deadline-based scheduling, with packet switching and table-driven multicast routing, to bound end-to-end delay and buffer requirements for time-constrained traffic while allowing best-effort traffic to capitalize on the low-latency routing and switching schemes common in modern parallel machines. To limit the cost of servicing time-constrained traffic, the router includes a novel packet scheduler that shares link-scheduling logic across the multiple output ports, while masking the effects of dock rollover on the representation of packet eligibility times and deadlines. Using the Verilog hardware description language and the Epoch silicon compiler, we demonstrate that the router design meets the performance goals of both traffic classes in a single-chip solution. Verilog simulation experiments on a detailed timing model of the chip show how the implementation and performance properties of the packet scheduler scale over a range of architectural parameters.

Parallel machines have the potential to satisfy the large computational demands of emerging real-time applications. These applications require a predictable communication network, where time-constrained traffic requires bounds on latency or throughput while good average performance suffices for best-effort packets. This paper presents a router architecture that tailors low-level routing, switching, arbitration and flow-control policies to the conflicting demands of each traffic class. The router implements deadline-based scheduling, with packet switching and table-driven multicast routing, to bound end-to-end delay for time-constrained traffic, while allowing best-effort traffic to capitalize on the low-latency routing and switching schemes common in modern parallel machines. To limit the cost of servicing time-constrained traffic, the router shares packet buffers and link-scheduling logic between the multiple output ports. Verilog simulations demonstrate that the design meets the performance goals of both traffic classes in a single-chip solution.