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Lisa Sather

dblp:13/3679 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
hardware verification		 0.011993
SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm · DAC 1993
Electronic design automation › physical design
layout verification		 0.011993
SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm · DAC 1993
Electronic design automation
physical design		 0.011993
SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm · DAC 1993
Electronic design automation › hardware verification and test › reverse engineering
subcircuit identification		 0.011993
SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm · DAC 1993

Methods — techniques the papers use, named apart from their topics

subgraph isomorphism · 0.0
YearPublicationVenuePosition
1993 SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm
abstract
The problem of finding subcircuits in a larger circuit arises in many contexts in computer-aided design.This is a problem currently solved using ad hoc Fellowship.,, of CMOS circuit examples.
Miles Ohlrich, Carl Ebeling, Eka Ginting, Lisa Sather
 DAC4