Current and future applications impose high demands on software-defined radio (SDR) platforms in terms of latency, reliability, and flexibility. This paper presents a heterogeneous SDR MPSoC with a hexagonal network-on-chip to address these issues. It features four data processing modules and a baseband processing engine for iterative multiple-input multiple-output (MIMO) receiving. Integrated memory controllers enable dynamic data flow mapping and application isolation. In a 4 x 4 MIMO application scenario, the MPSoC achieves a throughput of 232 Mbit/s with a latency of 20 μs while consuming 414 mW. It outperforms state-of-the-art platforms in terms of throughput by a factor of 4.

Emulating spiking neural networks on analog neuromorphic hardware offers several advantages over simulating them on conventional computers, particularly in terms of speed and energy consumption. However, this usually comes at the cost of reduced control over the dynamics of the emulated networks. In this paper, we demonstrate how iterative training of a hardware-emulated network can compensate for anomalies induced by the analog substrate. We first convert a deep neural network trained in software to a spiking network on the BrainScaleS wafer-scale neuromorphic system, thereby enabling an acceleration factor of 10000 compared to the biological time domain. This mapping is followed by the in-the-loop training, where in each training step, the network activity is first recorded in hardware and then used to compute the parameter updates in software via backpropagation. An essential finding is that the parameter updates do not have to be precise, but only need to approximately follow the correct gradient, which simplifies the computation of updates. Using this approach, after only several tens of iterations, the spiking network shows an accuracy close to the ideal software-emulated prototype. The presented techniques show that deep spiking networks emulated on analog neuromorphic devices can attain good computational performance despite the inherent variations of the analog substrate.

Many models of spiking neural networks heavily rely on exponential waveforms. On neuromorphic multiprocessor systems like SpiNNaker, they have to be approximated by dedicated algorithms, often dominating the processing load. Here we present a processor extension for fast calculation of exponentials, aimed at integration in the next-generation SpiNNaker system. Our implementation achieves single-LSB precision in a 32bit fixed-point format and 250Mexp/s throughput at 0.44nJ/exp for nominal supply (1.0V), or 0.21nJ/exp at 0.7V supply and 77Mexp/s, demonstrating a throughput multiplication of almost 50 and 98% energy reduction at 2% area overhead per processor on a 28nm CMOS chip.

Despite being originally inspired by the central nervous system, artificial neural networks have diverged from their biological archetypes as they have been remodeled to fit, particular tasks. In this paper, we review several possibilites to reverse map these architectures to biologically more realistic spiking networks with the aim of emulating them on fast, low-power neuromorphic hardware. Since many of these devices employ analog components, which cannot, be perfectly controlled, finding ways to compensate for the resulting effects represents a key challenge. Here, we discuss three different, strategies to address this problem: the addition of auxiliary network components for stabilizing activity, the utilization of inherently robust, architectures and a training method for hardware-emulated networks that, functions without, perfect, knowledge of the system's dynamics and parameters. For all three scenarios, we corroborate our theoretical considerations with experimental results on accelerated analog neuromorphic platforms.

This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction set extension tailored to fundamental data-intensive applications. We evaluate the MPSoC with typical database benchmarks focusing on scans and bitmap operations. When the processing elements operate on data stored in local memories, the chip consumes 250 mW and shows a 96x energy efficiency improvement compared to state-of-the-art platforms.

This brief presents a built-in self-calibration (BISC) technique for minimization of the total jitter in bang-bang all-digital phase-locked loops (ADPLLs). It is based on the addition of a monitoring phase-frequency detector (PFD) with tunable delay cells for the reference clock and the divider clock and a counter for this PFD output signal. This allows for on-chip binary comparison of the jitter distribution widths at the ADPLL PFD input, when ADPLL filter parameters are altered. Since only a relative comparison is performed, no accurate delay calibration is required. The statistical properties of this comparison of two random distributions are analyzed theoretically, and guidelines for circuit dimensioning are derived. The proposed method is used for BISC by adaption of the ADPLL filter coefficients. This allows for jitter minimization under process, voltage and temperature variations as well as gain and period jitter of the digitally controlled oscillator. The proposed calibration technique is verified by system simulations and measurements of a silicon prototype implementation in 28-nm CMOS technology.

This paper presents an all-digital pulse width modulator (PWM) for application in integrated DC-DC converters. Based on a multi-phase clock signal a PWM resolution of 62.5ps is achieved, resulting in up to 16-Bit PWM resolution at 4096ns period. The PWM signal duty cycle and period can be arbitrarily changed within a single cycle which allow efficient alldigital implementation of spread spectrum clocking schemes. The circuit has been implemented in 28nm SLP CMOS technology. It consumes 0.3mW when operating from a 1.0V supply.

The unbelievable properties of our information processing capabilities regarding the processing of big data, resilience, and energy efficiency are inspiration sources for the optimization and the rethinking of the principles of electronic information processing. Here, we present an approach of integrated circuits intended to solve chemical problems by active processing of chemical information.

A sensor system for measuring the power-ground (PG) noise in very large scale integrated circuits is presented. The proposed system utilizes sensor elements with standard cell dimensions enabling high spatial resolution voltage measurements of power and ground rails. Asynchronous sub-sampling is used to directly convert the analog signals into the digital domain inside the sensors to ensure precise waveform acquisition. Timing signals are derived from a all-digital phase-locked-loop (ADPLL) which guarantees accurate low-noise sampling of the supply waveforms. The sensor system has been implemented in a 28nm CMOS test chip. Simultaneous acquisition of voltage drop and ground bounce at 300 probe points within a 120μm × 120μm macro at 62.5 ps time and up to 250μV voltage resolution shows the capabilities of both, high spatial and high temporal resolution measurement of PG noise.

For neuromorphic ICs, the implemented synaptic dynamics play an important role in the complexity achievable when running networks on the overall IC. One of these ingredients for realistic dynamics are conductance-based synapses, which in contrast to current-based synapses let a neuron adapt in various ways to its input characteristics. Another ingredient is classical neuronal spike-frequency adaptation. Both are usually realized in fully-analog subthreshold circuits, making them hard to port to modern sub-100nm technologies. In contrast, we present a compact switched-capacitor (SC) model of a conductance-based synapse that can be widely configured to accurately depict e.g. NMDA, GABA or AMPA type synapses. The SC approach is inherently easy to port between technologies and its digital part benefits fully from technology scaling. We show how this synapse circuit can also be utilized to endow a neuron with spike-frequency adaptation (SFA).

Large-scale neuromorphic systems demand a sophisticated communication infrastructure to support several functionalities like configuration of neuron-and-synapse blocks, pulse stimulation, routing and tracing of the neural activity. This infrastructure is usually implemented around custom-designed FPGA systems. Performance requirements for these systems significantly increase when emulating the biological counterpart at an accelerated timescale. In this paper we characterize the capability of such a system to provide accurate long-term stimulation for emulated spiking networks and tracing of their activity. The design has a capacity of 1 billion timestamped events for both stimulation and tracing with a time resolution up to 48 ns. We characterize the communication flow in terms of throughput, transmission delay, packet loss and jitter. The results show that the implementation meets the needs of learning experiments, which is an important issue for state-of-the-art neuromorphic systems.

With neuromorphic hardware rapidly moving towards large-scale, possibly immovable systems capable of implementing brain-scale neural models in hardware, there is an emerging need to be able to integrate multi-system combinations of sensors and cortical processors over distributed, multisite configurations. If there were a standard, direct interface allowing large systems to communicate using native signalling, it would be possible to use heterogeneous resources efficiently according to their task suitability. We propose a UDP-based AER spiking interface that permits direct bidirectional spike communications over standard networks, and demonstrate a practical implementation with two large-scale neuromorphic systems, BrainScaleS and SpiNNaker. Internally, the interfaces at either end appear as interceptors which decode and encode spikes in a standardised AER address format onto UDP frames. The system is able to run a spiking neural network distributed over the two systems, in both a side-by-side setup with a direct cable link and over the Internet between 2 widely spaced sites. Such a model not only realises a solution for connecting remote sensors or processors to a large, central neuromorphic simulation platform, but also opens possibilities for interesting automated remote neural control, such as parameter tuning, for large, complex neural systems, and suggests methods to overcome differences in timescale and simulation model between different platforms. With its entirely standard protocol and physical layer, the interface makes large neuromorphic systems a distributed, accessible resource available to all.

Two terminal devices with switchable resistance have been of interest to electrical engineers for a long time, but only in the last few years has this attracted widespread attention. Recently a BiFeOe (BFO) capacitor-like metal-insulator-metal (MIM) structure was proposed as a synthetic synapse in neuromorphic systems, implementing voltage waveform driven spike timing dependent plasticity (STDP). Using a new device model that faithfully reproduces measurements of BFO-MIM structures we analyze how the switching characteristic affects the STDP learning window. Our simulations indicate that the gradual increase in the resistance change of BFO MIM structures result in a robust STDP with a biologically realistic learning window, whereas a distinct threshold followed by a steep hysteresis curve produce a narrow learning window and inflict strict operating conditions. Therefore we conclude that the steepness of the current voltage hysteresis curve is a fundamental characteristic to consider when designing synthetic synapses for neuromorphic hardware.

I. Demo Description Traditionally, neuromorphic ICs have integrated only reduced subsets of the rich repertoire of plasticity seen in biological preparations [1], [2]. The focus with respect to long term plasticity has been mostly on Spike-Time-Dependent Plasticity (STDP) [1]. Several ICs have also implemented forms of presynaptic short term dynamics, which filter synaptic pulse input, but have no influence on other timescales of plasticity. Here, we demonstrate an IC that implements short-term-, long-term-, and metaplasticity in an integrated way following [3], where these three different timescales interact to form the overall weight at the synapse. Fig. 1 shows an example presynaptic pattern with depression and the membrane trace as input for learning [3]. The resulting analog weight state shows the influence of presynaptic depression in the step increases, comparable to [1]. Also, different settings for the learning threshold exhibit a bias towards weight increase/decrease on a metaplastic (i.e. slow) timescale similar to [2]. The overall setup features several Maple-ICs of each 16 neurons and 512 of the above synapses, interlinked via FPGA-based pulse transmission. This allows network sizes of up to 200 neurons, sufficient to demonstrate the necessity for this type of learning for a range of computational neuroscience models.

Incremental delta-sigma ADCs are well suited for ambient light sensing applications due to their multiplex capability. Conventional ambient light sensor circuits consists of a current-to-voltage converter followed by an ADC. The proposed hybrid delta-sigma architecture integrates the current-to-voltage converter into the modulator loop. Circuit non-idealities of the current-to-voltage converter are thereby suppressed by noise shaping which greatly enhances the achievable resolution. Photodiode biasing as well as leakage current correction is realized by the fully differential current-to-voltage converter. The achievable resolution can be adapted by varying the conversion length.

This paper presents an all-digital phase-locked loop (ADPLL) clock generator for globally asynchronous locally synchronous (GALS) multiprocessor systems-on-chip (MPSoCs). With its low power consumption of 2.7 mW and ultra small chip area of 0.0078 mm2it can be instantiated per core for fine-grained power management like DVFS. It is based on an ADPLL providing a multiphase clock signal from which core frequencies from 83 to 666 MHz with 50% duty cycle are generated by phase rotation and frequency division. The clock meets the specification for DDR2/DDR3 memory interfaces. Additionally, it provides a dedicated high-speed clock up to 4 GHz for serial network-on-chip data links. Core frequencies can be changed arbitrarily within one clock cycle for fast dynamic frequency scaling applications. The performance including statistical analysis of mismatch has been verified by a prototype in 65-nm CMOS technology.

This paper presents a charge redistribution successive approximation A/D-Converter with 14 bit resolution designed in a 0.35 µm CMOS technology. An enhanced self-calibration technique is applied to correct mismatch of the binary weighted capacitors of a fully differential ADC. In contrast to previous presented solutions, no additional digital calculation is permanently necessary during conversion. Implementation and measurement results prove the concept and show main advantages regarding circuit area, digital complexity and calibration time.

This paper presents a power management architecture for MPSoCs that allows fast switching between multiple onchip supply voltage levels per core. Operation is based on distinct scenarios for power-up and supply level change, with individual numbers of pre-charge switches for supply noise reduction. The power management controller is highly configurable for adaption to a wide range of supply network parasitics in heterogeneous MPSoCs. This architecture has been validated by measurements in 65nm CMOS technology. Power-up and DVFS level changes can be performed in less than 20ns with reduced parasitic voltage drop of active cores.

This demonstration is based on the wafer-scale neuromophic system presented in the previous papers by Schemmel et. al. (20120), Scholze et. al. (2011) and Millner et. al. (2010). The demonstration setup will allow the visitors to monitor and partially manipulate the neural events at every level. They will get an insight into the complex interplay between packet-based and realtime communication necessary to combine continuous-time mixed-signal neural networks with a packet-based transport network. Several network experiments implemented on the setup will be accessible for user interaction.

Memristive devices have recently been proposed as efficient implementations of plastic synapses in neuromorphic systems. The plasticity in these memristive devices, i.e. their resistance change, is defined by the applied waveforms. This behavior resembles biological synapses, whose plasticity is also triggered by mechanisms that are determined by local waveforms. However, learning in memristive devices has so far been approached mostly on a pragmatic technological level. The focus seems to be on finding any waveform that achieves spike-timing-dependent plasticity (STDP), without regard to the biological veracity of said waveforms or to further important forms of plasticity. Bridging this gap, we make use of a plasticity model driven by neuron waveforms that explains a large number of experimental observations and adapt it to the characteristics of the recently introduced BiFeO$_3$ memristive material. Based on this approach, we show STDP for the first time for this material, with learning window replication superior to previous memristor-based STDP implementations. We also demonstrate in measurements that it is possible to overlay short and long term plasticity at a memristive device in the form of the well-known triplet plasticity. To the best of our knowledge, this is the first implementations of triplet plasticity on any physical memristive device.

Traditionally, the communication in neuromorphic VLSI systems has been done via parallel asynchronous transmission of Address-Event-Representations (AER) of neuron pulses. Recently, there has been a move towards greater event transmission speed via a serialization of the AER protocols. We give a live demonstration of a packet based synchronous serial AER infrastructure presented in a recent paper, which handles the complete off-wafer communication and configuration for a newly developed waferscale neuromorphic system, operating at a factor of 104faster than biological real-time. Pulse packets are routed from the host PC via Gbit Ethernet to an FPGA board, which forwards them to 4 purpose designed Digital Network ASICs (DNCs) on the same board. The DNCs buffer and sort the pulses, implementing 32 2GBit/s Low Voltage Differential Signaling (LVDS) interfaces to the neuromorphic circuits on the wafer. Pulse communication to other wafers is done via an FPGA- FPGA communication using 10 Gbit/s Aurora links.

In recent years, neuromorphic hardware systems have significantly grown in size. With more and more neurons and synapses integrated in such systems, the neural connectivity and its configurability have become crucial design constraints. To tackle this problem, we introduce a generic extended graph description of connection topologies that allows a systematical analysis of connectivity in both neuromorphic hardware and neural network models. The unifying nature of our approach enables a close exchange between hardware and models. For an existing hardware system, the optimally matched network model can be extracted. Inversely, a hardware architecture may be fitted to a particular model network topology with our description method. As a further strength, the extended graph can be used to quantify the amount of configurability for a certain network topology. This is a hardware design variable that has widely been neglected, mainly because of a missing analysis method. To condense our analysis results, we develop a classification for the scaling complexity of network models and neuromorphic hardware, based on the total number of connections and the configurability. We find a gap between several models and existing hardware, making these hardware systems either impossible or inefficient to use for scaled-up network models. In this respect, our analysis results suggest models with locality in their connections as promising approach for tackling this scaling gap.

This paper presents a switched capacitor voltage doubler as analog signal amplifier to increase the swing in low voltage electronics like PLLs. A signal is doubled with respect to a reference voltage which results in a wide signal swing exceeding the supply rails. An analytical expression of the transfer function, from which design equations for circuit parameters can be obtained, is derived including the effect of incomplete voltage settling due to finite switch resistances. The theory is validated by measurements of a voltage doubler as part of a PLL charge pump in 90nm CMOS technology.

The computational function of neural networks is thought to depend primarily on the learning/plasticity function carried out at the synapse. Neuromorphic circuit realizations have taken this into account by implementing a variety of synaptical processing functions, with most recent synapse circuits replicating some form of Spike Time Dependent Plasticity (STDP). However, STDP is being challenged by older rate-dependent learning rules as well as by biological experiments exhibiting more complex timing rules (e.g. spike triplets) as well as simultaneous rate- and timing dependent plasticity. In this paper, we present a circuit realization of a plasticity rule based on the postsynaptic neuron potential as well as the transmission profile of the presynaptic spike. To the best of our knowledge, this is the first circuit realization of synaptical behaviour which moves significantly beyond STDP, replicating the triplet experiments of Froemke and Dan, the combined timing and rate experiments of Sjoestroem et al., as well as conventional BCM behaviour.

This paper presents the design of a register file with 4 write and 6 read ports for an SDR multiprocessor in 65nm CMOS technology. A cell-based design (CBD) methodology is employed in which the circuit is partitioned into complex sub-cells, optimized on transistor level and layout. Each cell is completely characterized concerning timing and power for seamless integration into a semi-custom design flow. The CBD implementation shows 30% savings of power and 40% of area compared to a conventional semi-custom solution. The average power is 2.7mW from 1.0V supply and 300MHz operating frequency which is superior to previously published designs.

Research into the visual cortex and general neural information processing has led to various attempts to integrate pulse computation schemes in image analysis systems. Of interest is especially the robustness of representing an analogue signal in the phase or duration of a pulsed, quasi-digital signal, as well as the possibility of direct digital interaction, i.e. computation, among these signals. Such a computation can also achieve information compaction for subsequent processing stages. By using a pulse order encoding scheme motivated by dendritic pulse interaction, we will show that a powerful low-level feature and texture extraction operator, called pulsed local orientation coding (PLOC), can be implemented. Feature extraction results are being presented, and a possible VLSI implementation is detailed.

In this letter, we present an implementation of a neural microcircuit for image processing employing Hebbian-adaptive learning. The neuronal circuit utilizes only excitatory synapses to correlate action potentials, extracting the uncorrelated ones, which contain significant image information. This circuit is capable of approximating Gabor-like image filtering and other image processing functions.

A hardware implementation of an ADPLL-based clock generator is presented. The digital controlled oscillator (DCO) used in the ADPLL generates a clock signal with a high frequency resolution and a small jitter. The presented ADPLL has a fast acquisition and a large pull-in range. The whole design including the DCO has been described in synthesizable VHDL. It does not contain library specific cells, and can be synthesized independently of the standard cell library. Thus, it is portable and the time required to fit it for different semiconductor processes is reduced considerably. The design adaptation cost is limited to adjustment of a few constants in the VHDL-code. The presented design has been implemented in a V400BG432 VIRTEX FPGA and it has been synthesized using two different standard cell libraries (CMOS AMS 0.6 /spl mu/m and CMOS AMS 0.35 /spl mu/m). The maximum achievable clock frequency is 40 MHz using the FPGA and 52 MHz using the above mentioned standard cell libraries. The maximal lock-in time of the ADPLL is 30 reference clock cycles.

In this paper we propose an architecture for an image sensor with an embedded low-power analog preprocessing unit dedicated for convolution-type filtering. The convolution of the analog image data with the digital convolution kernel is realized using a sequential bit-wise principle. For the subsequent bit-shifted addition a modified current-mode pipelined A/D converter is suggested.