With the advancement of neural networks and computational power, significant progress has been made in the research of light field semantic segmentation. However, existing methods are always limited by capturing long-range global dependencies or secondary computational complexities, which restricts performance. In this paper, we investigate the recently proposed selective State Space Model (SSM) and introduce LFSSNet, a novel Light Field full-aperture efficient Semantic Segmentation Network. We design a series of light field visual feature selective scanning modules, enabling parallel and independent decoupled scanning of 4D complex light fields. These modules efficiently extract inherent spatial, angular, and bidirectional structural feature information from independent 2D slices of the 4D light fields. Additionally, we develop an SSM-attention Cross-fusion Enhancement Module, which further integrates the spatial-angular information and structural complementary information, achieving interactive enhancement of the fused features. Extensive experiments conducted on synthetic and real-world datasets validate the state-of-the-art performance of the proposed method. With 20 times the input data, a 6.73% improvement in accuracy, and a 4 times reduction in computational complexity, the proposed LFSSNet demonstrates its capability to achieve high-precision semantic segmentation utilizing full-aperture light field information while maintaining low computational complexity. Our code is available at: https://github.com/HNU-WQW/LFSSNet.

Efficiently aggregating 4D light field information to achieve accurate semantic segmentation has always faced challenges in capturing long range dependency information (CNN-based) and the memory limitations of quadratic computational complexity (Transformer-based). Recently, the Mamba architecture, which utilizes the state space model (SSM), has achieved high performance under linear complexity in various vision tasks. However, directly applying Mamba to 4D light field scanning will lead to an inherent loss of multi-spatial-angular information. To address the above challenges, we introduce LFSSMam, a novel Light Field Semantic Segmentation architecture based on the selective state space model (Mamba). Firstly, LFSSMam presents an innovative spatial-angular selective scanning mechanism to decouple and scan 4D multi-dimensional light field data. It separately captures the rich spatial context, complementary angular and structural information of light field 2D slices within the state space. In addition, we design an SSM-attention Cross-Fusion Enhance Module to perform preferential scanning and fusion across multi-spatial-angular-modal light field information, adaptively aggregating and enhancing the central view features. Comprehensive experiments on synthetic and real world datasets demonstrate that LFSSMam achieves leading edge SOTA (State-Of-The-Art) performance (with a 6.97% improvement to LF-based methods) while reducing memory and computational complexity. This work provides valuable guidance for the efficient modeling and application of multi-spatial-angular information in light field semantic segmentation. Our code is available at https://github.com/HNU-WQW/LFSSMam.

We present a new logic-simulation-based algorithm on verifying safety properties of large sequential hardware designs. This algorithm explores the search space defined by partitioned internal circuit nodes. Two powerful features are proposed to increase the effectiveness during search space exploration and counterexample generation for verifying safety properties. These include 1) new search space constituted by internal nodes instead of state variables and 2) static learning on multiple nodes to further enlarge the target. These two features are integrated with the following techniques during our simulation: incorporation of a BCP (Boolean constraint propagation) engine for multiple nodes implication and multiple-time-frame GA (genetic algorithm) search. Because only logic simulation is needed in our algorithm, the computational effort is low. Experimental results on large benchmark circuits have shown that this logic-simulation-based verifier achieves significantly better results compared with existing formal verification tools and simulation-based methods

This paper presents a new algorithm to extract characteristic flip-flops, which form a characteristic state set, using state-correlation information. The extracted characteristic state set allows us to focus on a significantly smaller set of flip-flops while ignoring other flip-flops, thereby simplifying the target problem and reducing state explosion in very large sequential circuits. Next, partitioning is applied only on the characteristic state variables, and partial state transition graphs (STGs) are built. During test generation, no specific fault or design error is targeted; instead, test vectors are generated using a twofold criteria: 1) whether the vector will expand the overall STGs and 2) whether this vector will break the relationship among flip-flops within the correlated sets. While generating vectors, state and transition exploration histories for each state group are maintained by dynamically constructing partial STGs for all state groups. By limiting a maximum size any state group can be, maintaining the complete state and transition exploration histories for each state group is feasible even for very large sequential circuits. Experiments showed that our extraction algorithm can reduce the original complete state set by up to 97%. In addition, with the reduced state variables, it achieves not only equal or better coverages for both stuck-at faults and design errors, the execution time is also significantly reduced due to the much fewer flip-flops that this paper needs to consider. For some large sequential circuits, highest coverages have been obtained

We present a new algorithm to extract characteristic flip-flops, which form a characteristic state set, using state correlation information. The extracted characteristic state set allows us to focus on a significantly smaller set of flip-flops while ignoring other flip-flops, thereby simplifying the target problem and reducing state explosion in very large sequential circuits. Next, partitioning is applied only on the characteristic state variables, and partial state transition graphs (STGs) are built. During test generation, test vectors are generated using a two-fold criteria: (1) whether the vector expand the overall STGs, and (2) whether this vector break the relationship among flip-flops within the correlated sets. Experiments showed that our extraction algorithm can reduce the original complete state set by up to 97%. In addition, with the reduced state variables, we achieve not only equal or better coverages for both stuck-at faults and design errors, the execution time is also significantly reduced due to the much smaller set of flip-flops. For some large sequential circuits, highest coverages have been obtained.

This paper introduces a new concept of state partitioning and state/transition exploration histories to generate test stimulus for the purpose of design validation. With our new state partitioning, during vector generation, state and transition exploration histories for each state group are maintained by dynamically constructing partial state transition graphs (STGs) for all state groups. By limiting a maximum size any state group can be, maintaining the complete state and transition exploration histories for each state group is feasible even for very large sequential circuits. While such histories are being collected, test vectors are generated using extracted spectral information from existing tests and genetic algorithm (GA) is used to explore new scenarios that are not in the histories. Experiments showed that much higher design error coverages together with smaller test sets are achieved with very short execution times.

We present a new automatic test pattern generation algorithm for sequential circuits by traversing the partitioned state spaces. The new features include: (1) nondisjoint state groups are obtained such that two different state groups may have common flip-flops, (2) partial state transition graphs (STGs) are constructed at run time for each state group, (3) spectral information for state variables are extracted and the spectral information of the state variables helps to identify the behavior of the flip-flops in the frequency domain. This information will help us to intelligently partition the state space. We focus only on the STGs for the flip-flops that are grouped together instead of building the STG for the entire circuit, and the ATPG tries to traverse all states and transitions within each partial STG. By exercising states visited and arcs traversed, the vectors generated often lead to the detection of hard faults. Since we limit a maximum size any state group can be, construction of partitioned STGs is feasible even for very large sequential circuits. Only logic simulation is needed in our ATPG; as a result, the execution time is greatly reduced while achieving high fault coverages compared with other test generators. For some large sequential circuits, highest fault coverages have been achieved.