Demo Data from VLDB 2026 / reviewers in the wild / expert
Toshihiko Yahara
dblp:13/5121
· DBLP profile ↗
7ranked-venue papers
0as first author
0since 2021 · last 1983
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
6 papers |
Electronic design automation · 88% Performance modeling and evaluation · 9% Integrated circuit design · 3% |
Topics — the 9 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 5 | 1982 | A consideration of the number of horizontal grids used in the routing of a masterslice layout · DAC 1982 An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 · DAC 1981 MILD - A cell-based layout system for MOS-LSI · DAC 1981 |
Electronic design automation › physical design
routing |
0.0 | 3 | 1982 | A consideration of the number of horizontal grids used in the routing of a masterslice layout · DAC 1982 A "grid-free" channel router · DAC 1980 MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks · DAC 1979 |
Electronic design automation › circuit simulation › timing simulation
delay simulation |
0.0 | 1 | 1983 | A multiple media delay simulator for MOS LSI circuits · DAC 1983 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 1983 | A multiple media delay simulator for MOS LSI circuits · DAC 1983 |
Electronic design automation › physical design
layout design |
0.0 | 1 | 1981 | An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 · DAC 1981 |
Electronic design automation › physical design › routing
channel routing |
0.0 | 1 | 1980 | A "grid-free" channel router · DAC 1980 |
Electronic design automation › physical design › routing › channel routing
gridless channel routing |
0.0 | 1 | 1980 | A "grid-free" channel router · DAC 1980 |
Electronic design automation › physical design › routing › message routing
hierarchical routing |
0.0 | 1 | 1979 | MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks · DAC 1979 |
Electronic design automation › physical design
gate array design |
0.0 | 1 | 1981 | An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 · DAC 1981 |
Methods — techniques the papers use, named apart from their topics
grid count prediction · 0.0constraint loop breaking · 0.0branch length minimization · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1983 | A multiple media delay simulator for MOS LSI circuits
Kaoru Okazaki, Tomoko Moriya, Toshihiko Yahara |
DAC | 3 |
| 1982 | A consideration of the number of horizontal grids used in the routing of a masterslice layoutabstractIn the masterslice LSI, since the wiring area is fixed, local wiring congestion is likely to occur, which may cause the occurrence of some wiring nets to be unroutable. If the number of grids used in the routing can be accurately predicted before the wire routing, it is possible to reduce greatly the occurrence of wiring nets to be unroutable. Masayuki Terai, Hajime Kanada, Koji Sato, Toshihiko Yahara |
DAC | 4 |
| 1981 | MILD - A cell-based layout system for MOS-LSI
Koji Sato, Takao Nagai, Mikio Tachibana, Hiroyoshi Shimoyama, Masaru Ozaki, Toshihiko Yahara |
DAC | 6 |
| 1981 | An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3
Chiyoji Tanaka, Shinichi Murai, Hiroo Tsuji, Toshihiko Yahara, Kaoru Okazaki, Masayuki Terai, Reiji Katoh, Mikio Tachibana |
DAC | 4 |
| 1981 | Efficient Logic Verification and Test Validation for MOS LSI Circuits
Kaoru Okazaki, Toshihiko Yahara |
ITC | 2 |
| 1980 | A "grid-free" channel routerabstractA grid-free channel router (termed GFR) is reported. GFR does not employ grid lines and can obtain better results than the fixed-grid method. Additionally, GFR has several optional functions, such as constraint loop breaking, total branch length minimization, constraint chain cutting and layer changing. The algorithms of these functions are outlined and results obtained by using them are presented. Koji Sato, Hiroyoshi Shimoyama, Takao Nagai, Masaru Ozaki, Toshihiko Yahara |
DAC | 5 |
| 1979 | MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks
Koji Sato, Takao Nagai, Hiroyoshi Shimoyama, Toshihiko Yahara |
DAC | 4 |