Thispaperpresents the descrtption of the architecture of the Chip Hierarchical Design System (CHDS) and details on the requiredTiming Driven Physical Design capabilities that have been defined to satisfy the physical design needs for 0.234 technologies and beyond.These requirements are intended to solve the challenges including the Design Productivity Crisis identijed by semiconductor industry, the shi$ in the design paradigm where the timing of a physical design will be dominated by interconnect effects, and the need for an integrated physicar design system which still supports "plug-and-play" through the use of EDA standard languages, moak's, and inte$aces.

Simple methods for enhancing PCM and DPCM monochrome pictures corrupted by transmission bit errors are described. For PCM signals the enhancement is achieved by operating exclusively on the corrupted image, without recourse to any sideinformation from the transmitter. The DPCM signals have simple protection codewords that increase the bit rate by 12 percent (if majority protection coding is used). Photographs of the original, corrupted, and enhanced images are presented, together with SNR as a function of percentage bit error rate (BER) for the corrupted and enhanced picture. For 0.1 < BER < 1.0, the SNR gains for PCM and DPCM are ≃ 10 and 18 dB, respectively. For BER <0.05 percent there is imperceptible picture degradation.

In a simulation of soft decision demodulation-interpolation for digital speech transmission, it has been noted that signal-to-noise ratio gains due to the technique are greater with nonadaptive and periodically adaptive quantizers than with instantaneously adaptive quantizers; further, the gains are greater with PCM than with differential PCM. Our results for nonadaptive PCM reinforce those in a recent analytical paper by Sundberg [1].