This demonstration shows a prototype chip of SLM (Scalable Logic Module) for a novel FPGA-IP embedded in various chips for edge computing. In this paper, the authors briefly describe the architecture of our FPGA-IP and the evaluation environment for the prototype chip.

Major cloud service providers have started employing field-programmable gate arrays (FPGAs) to implement high-performance and low-power-consumption cloud capability. However, building or utilizing an FPGA-enabled cloud is still challenging due to the lack of fundamental tools. In our previous work, we proposed an hCODE base system for managing portable accelerator IPs on different hardware. In this paper, we extend the previous work and introduce the hCODE 2.0, which is an open-source toolkit for building efficient FPGA-enabled clouds. First, we provide a fundamental toolkit to simplify HW project management and FPGA management at a cluster scale. Second, we implement on-chip resource virtualization and accelerator scheduling capabilities to show possibilities of improving FPGA utilization efficiency with our tools.

Field-programmable gate arrays (FPGAs) have demonstrated great speed performance and power efficiency advantages over conventional computers in various domains. However, it is still difficult for general software engineers to employ FPGA-based hardware accelerators because of the gap between hardware and software development methods. In this paper, we propose a heterogeneous computing oriented development environment (hCODE) to simplify the creation, sharing, and project integration of hardware accelerators. The hCODE defines hardware specifications and interface design rules. Hardware developers can provide designs that follow these rules, allowing software engineers to easily search, download, and integrate accelerators in their applications without caring about the details of the hardware.

A three-dimensional (3D) integration based on wafer-to-wafer bonding using through-silicon vias (TSVs) has been developed for the fabrication of new 3D large-scale integrated chips. To balance between cost and performance, and to explore 3D field-programmable gate array (FPGA) with realistic 3D integration processes, we propose spatially distributed and functionally distributed types of 3D FPGA architectures. The functionally distributed architecture consists of two wafers, a logic layer and a routing layer, and is stacked by a face-down process technology. Since vertical wires pass through microbumps, no TSVs are needed. In contrast, the spatially distributed architecture is divided into multiple layers with the same structure, unlike in the functionally distributed type. This architecture can be expanded to more than two layers by stacking multiples of the same die. The goal of this paper is to elucidate the advantages and disadvantages of these two types of 3D FPGAs. According to our evaluation, when only two layers are used, the functionally distributed architecture is more effective. When higher performance is achieved by using more than two layers, the spatially distributed architecture achieves better performance.

Most modern field-programmable gate arrays (FPGAs) employ a look-up table (LUT) as their basic logic cell. Although a k-input LUT can implement any k-input logic, its functionality relies on a large amount of configuration memory. As FPGA scales improve, the increased quantity of configuration memory cells required for FPGAs will require a larger area and consume more power. Moreover, the soft-error rate per device will also increase as more configuration memory cells are embedded. We propose scalable logic modules (SLMs), logic cells requiring less configuration memory, reducing configuration memory by making use of partial functions of Shannon expansion for frequently appearing logics. Experimental results show that SLM-based FPGAs use much less configuration memory and have smaller area than conventional LUT-based FPGAs.

High performance is required of many Android systems because embedded systems written for this operating system are used in several fields and rely on increasingly complicated processing. To accommodate this, we present a software/hardware (SW/HW) coprocessing platform implemented on a programmable system-on-a-chip (Xilinx Inc.: Zynq). This platform provides a unified architecture, extended OS kernel, application framework, and application distribution model to simplify the development and use of Android SW/HW coprocessing applications.

In this article, we present a design of a Blokus Duo engine for the ICFPT 2014 Design Competition. Our design is implemented on a Xilinx Zynq-7000 SoC ZC706 Evaluation Kit and we employ the minimax algorithm with alpha-beta pruning. The ARM processor runs the search algorithm, and the handwritten hardware accelerator calculate within 1 second under the competition constraint. One of the keys to a stronger Blokus Duo player is to evaluate more states of a game; our Blokus Duo engine evaluates 12.3 times as many nodes of a game search tree as the Intel Core i7-3770T.

The most widely used open-source field-programmable gate array (FPGA) placement and routing tool is VPR, which can define the target FPGA, perform placement and routing, and report area and timing information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, for most newly developed FPGA architectures, VPR cannot support them directly. Modifying the C-coded VPR for using it to evaluate a number of new architectures requires a long time. Second, the accuracy of the VPR performance results is not enough for the evaluation of a complete synthesizable FPGA IP in the design that targets the productions of LSI. We propose a FPGA design framework that in particular improves FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely EasyRouter. EasyRouter is developed using the C# language. When an object-oriented programming method is used, the source codes are fewer and easier manage compared to VPR, which shortens the development time. By using simple HDL templates, EasyRouter can automatically generate entire chip HDL codes and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CADs with high accuracy and reliability.

In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their computer-aid design (CAD) for intellectual property (IP) cores in system large-scale integration (LSI). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are regular tile structure, spare modules and bypass wires for fault avoidance, and configuration mechanism for single-cycle reconfiguration. In addition, we develop routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGA and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 2.2 times the area and 1.3 times the delay compared with conventional FPGA architectures. At the same time, conventional FP-GAs cannot tolerate faults, whereas our architectures perform with a 90% success rate in fault avoidance for a ratio of faulty tiles of 1% or less.

Conventional FPGA design and implementation processes involve two separate flows. The FPGA architecture is determined by academic FPGA design flow. However, in the implementation phase, commercial VLSI design flow are used. In this research, we propose an FPGA design framework in order to improve synthesizable FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter, which can bridge the two flows efficiently. With this design flow, accurate physical information can be reported when a new FPGA IP architecture is evaluated with reliable commercial VLSI CADs.

In recent years, as VLSI process scales have developed into deep sub-micrometer dimensions, routing delay problems have become critical. For reconfigurable logic devices (RLDs) like field-programmable gate arrays (FPGAs) in particular, routing resources occupy major parts of the available area and hinder performance. In order to balance cost and performance, and to explore 3D FPGA architectures with realistic 3D LSI processes, we proposed a novel two-layers 3D FPGA architecture based on 3D connections on logic block input and output pins. Evaluation shows that this novel RLD with two layers of 3D routing architecture uses 48.75% less on-board area and 30.54% less critical path delay than does a conventional 2D 4-lookup table island-style FPGA on average.

Current commercial SRAM-based FPGAs, such as Virtex-6 and Stratix-V, can perform dynamic partial reconfiguration (DPR). Partial reconfiguration (PR) can change a part of the device without reconfiguring the whole chip. Thus, we can switch the part of system with continuing the operation. However, the authorized design flow by Xilinx creates different PR bit stream (PRB) for each partially reconfigurable region (PRR) even if it is the same circuit. This indicates that N × M PRBs must be prepared to implement M types modules on N PRRs. This increases design time and memory usage to store PRBs. This paper presents a uniforming design technique for PRRs to relocate a PRB among them. In addition, uniformed PRRs can be used to implement large module by combining adjacent PRRs. In this work, we use Xilinx Virtex-6 XC6VLX240T and Integrated Software Environment 13.3 (ISE) to verify the proposed technique.

Although redundancy techniques are generally used to provide fault tolerance for the system large scale integrations (LSIs), these techniques have significantly costs. However, field programmable gate arrays (FPGAs) can easily provide high reliability due to their reconfiguration ability. The present paper proposes an effective fault detection method for the global interconnects of the FPGA. In the proposed method, by combining different kinds of test patterns, the fault resources can be identified. We also developed placement and routing tools to avoid fault resources in two cases, namely, tile-level avoidance and multiplexer-level avoidance. In the evaluation of the proposed technique, the proposed detection method diagnosed a defect multiplexer with six test configurations. We found that the fault FPGA can achieve the same performance as normal FPGA in multiplexer-level avoidance.

SRAM-based field programmable gate arrays (FPGAs) are vulnerable to soft-error. To improve circuit dependability, various dependable design techniques have been studied. By the same token, evaluation techniques are required to ensure dependability. The most popular evaluation technique is reconfiguration-based fault-injection (FI) analysis. However, most FI analyses are inadequate for the evaluation of a dependable circuit because they don't consider fault accumulation. The critical issue is the reconfiguration time for injecting many faults. This paper presents an FI analysis system using frame-based partial reconfiguration and a bootstrap method to accelerate evaluation. As a result, our system can accelerate FI time by about a factor of 5 ~ 10 relative to the full-reconfiguration FI system. Further, the number of reconfiguration times is reduced to one out of several dozen by applying the bootstrap method.

SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU), which is induced by radiation effect. This paper presents a technique for ensuring reliable softcore processor implementation on SRAM-based FPGAs. Although an FPGA is susceptible to SEUs, these faults can be corrected as a result of its reconfigurability. We propose techniques for SEU mitigation and recovery of a softcore processor using triple modular redundancy (TMR) and partial reconfiguration (PR) with state synchronization. By carrying out an experiment, we confirm that a faulty softcore processor can be recovered and synchronized with other softcore processors. The proposed technique requires 4.315 times the resource usage and 62.491% of the operating frequency of the base processor. However, the proposed recovery process only takes 6 μs under TMR and PR. As a result of reliability estimation, the proposed system achieved about 2.713 times longer MTBF comparing with the previous system.

The performance of field-programmable gate arrays (FPGAs) has been significantly improved due to a new process technology. However, several problems have arisen in the new generation FPGAs. Specifically, the issue of power consumption is a serious issue, because FPGAs have many routing resources. We report on the improvement of both the FPGA routing structure and electronic design automation (EDA) tools in order to solve this issue. In order to reduce the power consumption, high activity nets are assigned to low load lines, which is the routing structure used for small-world networks in FPGAs. In addition, the clustering and routing algorithms of the EDA tools are improved to complement the routing structure. This report demonstrates that the power can be reduced. Based on evaluation results, a maximum power consumption improvement of 48.4% was obtained, and the average improvement was 22.9% when using the proposed routing structure and EDA tools.

The present paper describes a technique for ensuring re- liable softcore processor implementation on SRAM-based field programmable gate arrays (FPGAs), which can handle the effects of single event upsets (SEUs). We propose the triple modular redundancy (TMR) scheme coupled with dynamic partial reconfiguration to remove SEUs from the configuration memory of the FPGA. Although the FPGA is subject to SEUs, these errors can be corrected as a result of its reconfigurability. Furthermore, we consider the synchronization after a partial reconfiguration using an interrupt process of an RTOS. Experimental results reveal that one faulty softcore processor is recovered and synchronized with the other softcore processors. The present study demonstrates that a softcore processor can recover from an SEU using the proposed dynamic partial reconfiguration and the synchronization process.

This work presents a dynamically reconfigurable platform called EXPRESS-1, which uses the commercially available embedded processor FPGA. The system makes the most of a fully reconfigurable logic part to explore the area of fine-grained reconfigurable computing. A dynamic reconfiguration mechanism is implemented utilizing a real-time operating system, so device reconfiguration in response to application demand works without suspending other services. EXPRESS-1 features a transparent execution mechanism. Whether a function is executed by the hardware or software, the mechanism frees users from awareness of its execution manner. Furthermore, there is no need to explicitly specify reconfiguration commands into a program because the system determines if reconfiguration is needed based on current conditions. The development of EXPRESS-1 and the runtime reconfiguration mechanism of the fully reconfigurable logic are described. System capabilities are also reported through fundamental evaluations with some practical applications such as JavaVM, encryption processing, and image processing.

SIMP is a novel multiple instruction-pipeline parallel architecture. It is targeted for enhancing the performance of SISD processors drastically by exploiting both temporal and spatial parallelisms, and for keeping program compatibility as well. Degree of performance enhancement achieved by SIMP depends on; i) how to supply multiple instructions continuously, and ii) how to resolve data and control dependencies effectively. We have devised the outstanding techniques for instruction fetch and dependency resolution. The instruction fetch mechanism employs unique schemes of; i) prefetching multiple instructions with the help of branch prediction, ii) squashing instructions selectively, and iii) providing multiple conditional modes as a result. The dependency resolution mechanism permits out-of-order execution of sequential instruction stream. Our out-of-order execution model is based on Tomasulo's algorithm which has been used in single instruction-pipeline processors. However, it is greatly extended and accommodated to multiple instruction pipelining with; i) detecting and identifying multiple dependencies simultaneously, ii) alleviating the effects of control dependencies with both eager execution and advance execution, and iii) ensuring a precise machine state against branches and interrupts. By taking advantage of these techniques, SIMP is one of the most promising architectures toward the coming generation of high-speed single processors.