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Donald L. Epley

dblp:13/682 · also Don Epley · DBLP profile ↗
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3ranked-venue papers
2as first author
0since 2021 · last 1978
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorHuman-computer interaction and ubiquitous computing · 1 · 1 first-authorApplied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Memory systems · 53% Parallel and multicore computing · 27% Embedded and real-time systems · 15%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
memory hierarchy
0.011972
Memory Requirements in a Multiprocessing Environment · J. ACM 1972
Parallel and multicore computing
multiprocessor system
0.011972
Memory Requirements in a Multiprocessing Environment · J. ACM 1972
Memory systems › memory hierarchy
two-level memory system
0.011972
Memory Requirements in a Multiprocessing Environment · J. ACM 1972
Embedded and real-time systems › real-time scheduling
multiprocessor scheduling
0.011968
R68-5 Models of Computational Systems-Cyclic to Acyclic Graph Transformations · IEEE Trans. Computers 1968
Performance modeling and evaluation
system modeling
0.011968
R68-5 Models of Computational Systems-Cyclic to Acyclic Graph Transformations · IEEE Trans. Computers 1968

Methods — techniques the papers use, named apart from their topics

computation graph · 0.0
YearPublicationVenuePosition
1978 A two-semester course sequence in introductory programming using PL/1 - a rationale and overview
abstract
In 1975 a major curriculum revision which converted an introductory first course using FORTRAN and a second course using PL/i into a two-semester PL/i sequence was made.The initial rationale and motivation, including an analysis of the potential audience and alternatives, is discussed.An overview of the individual courses, the distribution of topics, and our experience with the two courses is given.A review of this three-year old decision and another analysis of alternatives, especially in the light of the trend towards PASCAL and increasing emphasis on program verification, is made.Our conclusion is based on language-independent factors arising from our attitude towards programming and certain larger curriculum issues and is that our PL/i sequence should be retained.
Donald L. Epley, Ted Sjoerdsma
SIGCSE1
1972 Memory Requirements in a Multiprocessing Environment
abstract
Main memory and intermemory data transmission rate requirements of two-level memory multiprocessor systems are characterized.Operational software is modeled by computation graphs.For a fixed processing schedule, independent bounds on the main memory M and the data transmission rate C, required to insure that the processing will follow the specified schedule, are determined.Tradeoffs between M and C are completely specified by determination of the family of (M, C) pairs, any member of which will guarantee that the fixed schedule will be followed.The notion of an optimal pair (M, C) is introduced and the optimal pairs are also found.The interrelationship between values of (M, C) pairs and schedules is briefly explored througb modification of specified schedules.
Y. E. Chen, Donald L. Epley
J. ACM2
1968 R68-5 Models of Computational Systems-Cyclic to Acyclic Graph Transformations
abstract
These three papers, based upon the first author's Ph. D. dissertation, are concerned with the problem of assignment and sequencing of computations on multiprocessor or parallel computer systems. Although individually the papers suffer from the usual abstracting difficulties, the results are significant and warrant serious study by readers interested in computer system modeling and analysis.
Donald L. Epley
IEEE Trans. Computers1