A novel 4-way pipelined processing architecture is presented for three-step search block-matching motion estimation. For the 4-way pipelined processing, we have developed a method which divides the current block and search area into 4 subregions respectively and processes them concurrently. Also, we have developed a memory partitioning method to access pixel data from the 4 subregions concurrently without memory conflict. The architecture has been designed and simulated with C language and VHDL. Simulation results show that the proposed architecture achieves a high performance for real time motion estimation

Presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a graph specification with timing constraints. A timing analysis extracts the timed concurrency and timed causality relations directly from the specification. Then, a hazard-free implementation of the specification is synthesized by analyzing precedence graphs which are constructed by using the timed concurrency and timed causality relations. The major result of this work is that the method does not suffer from the state explosion problem, in practice achieves significant reductions in synthesis time for the specifications which have a large state space, and generates synthesized circuits that have nearly the same area as compared to previous timed circuit methods. In particular, this paper shows that a timed circuit-not containing circuit hazards under given timing constraints-can be found by using the relations between signal transitions of the specification. Moreover, the relations can be efficiently found using a heuristic timing analysis algorithm. By allowing significantly larger designs to be synthesized, this work is a step toward the development of high-level synthesis tools for system level asynchronous circuits.

This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a deterministic graph specification with timing constraints. A timing analysis extracts the timed concurrency and timed causality relations between any two signal transitions. Then, a hazard-free implementation of the specification is synthesized by analyzing precedence graphs which are constructed by using the timed concurrency and timed causality relations. The major result of this work is that the method does not suffer from the state explosion problem, achieves significant reductions in synthesis time, and generates synthesized circuits that have nearly the same area as compared to previous timed circuit methods. In particular, this paper shows that a timed circuit-not containing circuit hazards under given timing constraints-can be found by using the relations between signal transitions of the specification. Moreover, the relations can be efficiently found using a heuristic timing analysis algorithm. By allowing significantly larger designs to be synthesized, this work is a step towards the development of high-level synthesis tools for system level asynchronous circuits.

This paper presents an algorithm which synthesises gate-level speed-independent control circuits directly from signal transition graphs (STGs) by analyzing the relations between the signal transitions in the STG. It uses an exhaustive approach to improve the performance of the synthesized circuit in terms of the circuit area and speed. The experimental results show that our algorithm yields more efficient circuits than the existing works in reasonable time.

This paper presents a new algorithm which synthesizes a speed-independent circuit from a deterministic Signal Transition Graph (STG) representation which satisfies safeness, liveness and unique state coding property. Existing works translate a higher level description such as a nondeterministic STG representation into a State Graph (SG) representation and then translate the SG representation into a speed-independent circuit. In contrast our algorithm synthesizes a speed-independent circuit directly from the STG representation by analyzing the relations between the signal transitions in the representation. It turns out that our algorithm yields more efficient circuits than the existing works. Also, it turns out that the run time of our algorithm is, in most cases, faster than that of the existing works.>