SCADA alarm management poses many challenges for power grid control room operators. Vast quantities of information must be managed and filtered by human operators to identify the specific alarm of interest so that system issues can be promptly addressed. The use of knowledge based systems and decision support systems to assist in industrial decision making is well established but comes with heavy cost burdens for development and maintenance. This work demonstrates a possible approach to addressing this cost issue by utilising large language models (LLMs) to parse SCADA alarms and extract information to construct a knowledge base in the form of a knowledge graph. This knowledge base can then be used to construct a decision support system suitable for control room operators to make plain language queries that assist in their problem solving. The decision support approach facilitates better and faster decision making assisting the effective management of electrical distribution networks by control room operators. The case study shown in this work demonstrates that LLMs show promising capacity for knowledge base constructions and have the potential to unlock easy access and insights from large volumes of SCADA alarm data.

In this paper, we present our approach for quantifying uncertainty in our dual-embedding based entity extraction system. First, we review the state-of-the-art uncertainty estimation methods. We then present our entity extraction system and discuss practical challenges of applying each of the uncertainty estimation solutions to our system. Finally, we present our uncertainty estimate approach and its performance in production. Our goal is to present the challenges and concerns that one should consider while designing an uncertainty estimation solution in the real world and, therefore, help the research community to develop more practical uncertainty estimation solutions.

Intratumour heterogeneity is increasingly recognized as a frequent problem for cancer treatment as it allows for the evolution of resistance against treatment. While cancer genotyping becomes more and more established and allows to determine the genetic heterogeneity, less is known about the phenotypic heterogeneity among cancer cells. We investigate how phenotypic differences can impact the efficiency of therapy options that select on this diversity, compared to therapy options that are independent of the phenotype. We employ the ecological concept of trait distributions and characterize the cancer cell population as a collection of subpopulations that differ in their growth rate. We show in a deterministic model that growth rate-dependent treatment types alter the trait distribution of the cell population, resulting in a delayed relapse compared to a growth rate-independent treatment. Whether the cancer cell population goes extinct or relapse occurs is determined by stochastic dynamics, which we investigate using a stochastic model. Again, we find that relapse is delayed for the growth rate-dependent treatment type, albeit an increased relapse probability, suggesting that slowly growing subpopulations are shielded from extinction. Sequential application of growth rate-dependent and growth rate-independent treatment types can largely increase treatment efficiency and delay relapse. Interestingly, even longer intervals between decisions to change the treatment type may achieve close-to-optimal efficiencies and relapse times. Monitoring patients at regular check-ups may thus provide the temporally resolved guidance to tailor treatments to the changing cancer cell trait distribution and allow clinicians to cope with this dynamic heterogeneity.

Leakage power minimization is critical to semiconductor design in nanoscale CMOS. On the other hand increasing variability with scaling adds complexity to the leakage analysis problem. In this work we seek to achieve tractability in Monte Carlo-based statistical leakage analysis. A novel approach for fast and accurate statistical leakage analysis considering inter-die and intra-die components is proposed. We show that the optimal way to select samples, to capture intra-die variation accurately, is according to the probability distribution function of total process variation. Intelligent selection of samples is performed using a Quasi Monte Carlo technique. Results are presented for benchmarks with sizes varying from approximately 5,000 to 200,000 gates. The largest benchmark with 198461 gates is evaluated in 3 minutes with the proposed approach compared to 23 hours for random sampling with comparable accuracy. Compared to a conventional analytical approach using Wilkinson's approximation, the proposed technique offers superior accuracy while maintaining efficiency. State dependence and multiple sources of variation are considered and the approach is scalable with number of process parameter variables for standard cell characterization cost. We also show reduction in sample size to meet target accuracy for computing leakage distribution due to the inter-die component only when compared to random selection of samples.

Due to aggressive scaling of device feature size to improve circuit performance in the sub-wavelength lithography regime, both diffusion and poly gate shapes are no longer rectilinear. Diffusion rounding occurs most notably where the diffusion shapes are not perfectly rectangular, including common L and T-shaped diffusion layouts to connect to power rails. This paper investigates the impact of the non-rectilinear shape of diffusion (i.e., sloped diffusion or diffusion rounding) on circuit performance (delay and leakage). Simple weighting function models for Ionmiddot and Ioffto account for the diffusion rounding effects are proposed, and compared with TCAD simulation. Our experiments show that diffusion rounding has an asymmetric characteristic for Ioff due to the differing significance of source/drain junctions on device threshold voltage. Therefore, we can model Ionmiddot and Ioffas a function of slope angle and direction. The proposed models match well with TCAD simulation results, with less than 2% and 6% error in Ionmiddot and Ioff, respectively.

Increasing levels of process variation in current technologies have a major impact on power and performance and result in parametric yield loss. In this paper, we develop an efficient gate-level approach to accurately estimate and optimize the parametric yield, defined by leakage power and delay limits, by finding their joint probability distribution function. We consider inter-die variations, as well as intra-die variations, with correlated and random components. The correlation between power and performance arises due to their dependence on common process parameters and is shown to have a significant impact on the yield, particularly in high-frequency bins. We then propose a new heuristic approach to incrementally compute the gradient of yield with respect to gate sizing and gate-length biasing in the circuit with high efficiency and accuracy. We show how this gradient information can be effectively used by a nonlinear optimizer to perform yield optimization. The proposed yield-analysis approach is compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%. The proposed optimization approach is implemented and tested, and we demonstrate an average yield increase of 40% using gate sizing (as compared to a deterministically optimized circuit). Even higher improvements are demonstrated when both gate sizing and gate-length-biasing techniques are used.

Line-end shortening (LES) has always been considered a catastrophic failure in circuits. However, we find that a device with some LES can continue to function correctly. Such devices have large drive current and reduced capacitance at the expense of much higher leakage current. In this paper, we investigate the power and performance characteristics of devices with LES. Our simulations show that LES does not always cause catastrophic failure of device functionality. However, in this regime LES can lead to parametric failures, aspects of which we investigate .

Scaling device geometries have caused leakage-power consumption to be one of the major challenges of deep sub-micron design and a major source for parametric yield loss. We propose a library optimization approach involving generation of additional variants for each cell master, by biasing gate-lengths of devices. We employ transistor-level gate-length assignment to exploit asymmetries in standard cell circuit topology as well slack distribution of the design. The enhanced library is used by a power optimizer to reduce design leakage without violating any timing constraints. Such transistor-level optimization of cell libraries offers significantly better leakage-delay tradeoff than simple cell-level biasing (CLB) proposed previously. Experimental results on benchmarks show transistor-level biasing (TLB) can improve the CLB leakage optimization results by 8-17%. There is a corresponding improvement in design leakage distribution as well.

Increasing levels of process variation in current technologies have a major impact on power and performance, and result in parametric yield loss. In this work we develop an efficient gate-level approach to accurately estimate the parametric yield defined by leakage power and delay constraints, by finding the joint probability distribution function (jpdf) for delay and leakage power. We consider inter-die variations as well as intra-die variations with correlated and random components. The correlation between power and performance arise due to their dependence on common process parameters and is shown to have a significant impact on yield in high-frequency bins. We also propose a method to estimate parametric yield given the power/delay jpdf that is much faster than numerical integration with good accuracy. The proposed approach is implemented and compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%.

With the increased significance of leakage power and performance variability, the yield of a design is becoming constrained both by power and performance limits, thereby significantly complicating circuit optimization. In this paper, we propose a new optimization method for yield optimization under simultaneous leakage power and performance limits. The optimization approach uses a novel leakage power and performance analysis that is statistical in nature and considers the correlation between leakage power and performance to enable accurate computation of circuit yield under power and delay limits. We then propose a new heuristic approach to incrementally compute the gradient of yield with respect to gate sizes in the circuit with high efficiency and accuracy. We then show how this gradient information can be effectively used by a non-linear optimizer to perform yield optimization. We consider both inter-die and intra-die variations with correlated and random components. The proposed approach is implemented and tested and we demonstrate up to 40% yield improvement compared to a deterministically optimized circuit.

This paper presents a novel approach towards the simultaneous Vt-assignment and gate-sizing problem. This inherently discrete problem is formulated as a continuous problem, allowing it to be solved using any of several widely available and highly efficient non-linear optimizers. We prove that, under our formulation, the optimal solution has discrete Vts assigned to almost every gate, thus eliminating the need for a sophisticated snapping heuristic. We show that this technique performs dual-Vt assignment and gate sizing in a very efficient manner. Compared to a sensitivity based method, we achieve average leakage savings of 31% and average total power savings of 7.4% with very efficient runtimes.

High performance digital circuits require long bus lines to operate at very high frequencies, necessitating a large number of repeaters to be inserted along these lines. Power consumed by repeaters, particularly that contributed by subthreshold leakage, is becoming a major consideration in digital design. We compare several threshold voltage assignment schemes to reduce runtime leakage power in buffers. We explore trade-offs between dynamic and static power by selectively mixing high and low Vt devices within a pull-up or pull-down network. We propose an activity-dependent hybrid Vt assignment scheme that can be applied across a bus. These configurations are shown to reduce total power by up to 38% and runtime leakage by up to 48%, with negligible design or area overhead.