Local defect patterns (LDP) in wafer maps are usually induced by problems in the manufacturing process. Therefore, defect pattern recognition is useful for root cause analysis, which is very important for yield optimization. Machine learning (ML) based methods can achieve good LDP recognition rate. In general, these techniques are designed to identify spatial patterns, which may not directly linked to the root cause. Besides, ML methods are more time-consuming because of the training process. In this paper, we propose to apply a rule-based method for LDP classification such that the recognized patterns are explainable. Experimental results show that the proposed method achieves roughly the same level of accuracy as other ML methods while the exaction time is much faster.

We propose an automatic wafer defect maps detection method based on unsupervised learning. There is no need for human labeling, and similar defect clusters are identified automatically without human intervention. As a result, the process is less error-prone. Whenever the wafer test result of a WUT is available, it can be compared immediately with existing clusters. If the wafer map matches one of the known defect patterns, then RCA can be done efficiently.

Wafer map defect pattern recognition provides a visual way for root cause analysis and yield learning. Specially, recognizing grid, including line and intersection point types in wafer defect patterns is a challenging problem for process and test engineers. Grid is a repeating defect pattern that appears in multiple wafers, so identifying such patterns helps to trace the root cause of defects for yield ramp up. In this paper, we propose a grid pattern recognition methodology taking into account both partial and hidden grid patterns. Hidden defective dies are dies in the grid contour that pass wafer test. However, such dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the potential defective dies in hidden grid patterns and mark them as faulty. As a result, the reliability of products and test cost can be significantly improved. In this paper, we propose a systematic methodology to search for hidden grid patterns in wafers. A five-phase method is developed to enhance wafer maps such that automatic defect pattern recognition can be carried with high accuracy. Experimental results show the proposed method can achieve 100% prediction accuracy for all grid types, and also achieve 96.45% by Extremely Randomized Trees for all nine common wafer defect types averagely.

Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. As a result, test quality, reliability and yield could be improved accordingly. Wafer test data contain site-dependent information regarding test configurations in automatic test equipment, including effective load push force, gap between probe and load-board, probe tip size, probe-cleaning stress, etc. Our method analyzes both the test paths and site-dependent test characteristics to identify test-induced defects. Experimental results achieve 96.83% prediction accuracy of six NXP products, which show that our methods are both effective and efficient.

We propose a machine learning based method targeted for accurate wafer defect map classification. The proposed method is referred to as TestDNA-E, as it applies ensemble learning based on improved TestDNA features. Experimental results show that the proposed method achieves high hit rate for each defect type and overall accuracy.

Wafer defect maps exhibit spatial failure pattern recognition for root cause analysis to improve defect diagnosis resolution and yield learning conventionally. We apply further product-driven test items to propose a wafer-level test methodology to generate a DNA-like wafer defect signature to identify wafer defects. Experience results show that our TestDNA are both effective and efficient, including the tight relation with traditional wafer defect patterns, high prediction accuracy over 90%, and improved lower non-pattern ratio from over 95% to around 11%.

Given a graph${\mbi{G}}$and a non-negative integer${{g}}$, the${{g}}$-extra connectivity (resp.${{g}}$-extra edge connectivity) of${\mbi{G}}$is the minimum cardinality of a set of vertices (resp. edges) in${\mbi{G}}$, if it exists, whose deletion disconnects${\mbi{G}}$and leaves each remaining component with more than${{g}}$vertices. This study shows that the 3-extra connectivity (resp. 3-extra edge connectivity) of an${\mbi{n}}$-dimensional folded hypercube is${4}{{n}} - {5}$for${{n}} \geq {6}$(resp.${4}{{n}} - {4}$for${{n}} \geq {5}$). This study also provides an upper bound for the${{g}}$-extra connectivity on folded hypercubes for${{g}} \geq {6}$.

Using the comparison diagnosis model, this study proposes some useful sufficient conditions for determining the strong diagnosability ts(G) and the conditional diagnosability tc(G) of a system G. Applying these results to an n-dimensional folded hypercube FQnshows that ts(FQn) = n + 1 for n ≥ 5 and tc(FQn) = 3n - 2 for n ≥ 5. Moreover, tc(FQ3) = 3 and tc(FQ4) = 7.