Demo Data from VLDB 2026 / reviewers in the wild / expert
Miguel A. Gonzalez-Mesa
dblp:130/5842
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 60% Distributed systems · 40% | |
| Software engineering, system software, and programming languages
1 paper |
Concurrent programming · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Distributed systems
concurrency control |
0.2 | 1 | 2014 | Effective Transactional Memory Execution Management for Improved Concurrency · ACM Trans. Archit. Code Optim. 2014 |
Distributed systems › distributed database › commit protocol
distributed commit |
0.2 | 1 | 2014 | Effective Transactional Memory Execution Management for Improved Concurrency · ACM Trans. Archit. Code Optim. 2014 |
Parallel and multicore computing
parallel programming models |
0.2 | 1 | 2014 | Effective Transactional Memory Execution Management for Improved Concurrency · ACM Trans. Archit. Code Optim. 2014 |
Parallel and multicore computing › transactional memory
software transactional memory |
0.2 | 1 | 2014 | Effective Transactional Memory Execution Management for Improved Concurrency · ACM Trans. Archit. Code Optim. 2014 |
Parallel and multicore computing
transactional memory |
0.2 | 1 | 2014 | Effective Transactional Memory Execution Management for Improved Concurrency · ACM Trans. Archit. Code Optim. 2014 |
Concurrent programming
memory models |
0.1 | 1 | 2014 | Effective Transactional Memory Execution Management for Improved Concurrency · ACM Trans. Archit. Code Optim. 2014 |
Methods — techniques the papers use, named apart from their topics
simulation · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | Effective Transactional Memory Execution Management for Improved ConcurrencyabstractThis article describes a transactional memory execution model intended to exploit maximum parallelism from sequential and multithreaded programs. A program code section is partitioned into chunks that will be mapped onto threads and executed transactionally. These transactions run concurrently and out of order, trying to exploit maximum parallelism but managed by a specific fully distributed commit control to meet data dependencies. To accomplish correct parallel execution, a partial precedence order relation is derived from the program code section and/or defined by the programmer. When a conflict between chunks is eagerly detected, the precedence order relation is used to determine the best policy to solve the conflict that preserves the precedence order while maximizing concurrency. The model defines a new transactional state called executed but not committed . This state allows exploiting concurrency on two levels: intrathread and interthread. Intrathread concurrency is improved by having pending uncommitted transactions while executing a new one in the same thread. The new state improves interthread concurrency because it permits out-of-order transaction commits regarding the precedence order. Our model has been implemented in a lightweight software transactional memory system, TinySTM, and has been evaluated on a set of benchmarks obtaining an important performance improvement over the baseline TM system. Miguel A. Gonzalez-Mesa, Eladio Gutiérrez, Emilio L. Zapata, Oscar G. Plata |
ACM Trans. Archit. Code Optim. | 1 |
| 2013 | Exploring Irregular Reduction Support in Transactional Memory
Miguel A. Gonzalez-Mesa, Ricardo Quislant, Eladio Gutiérrez, Oscar G. Plata |
ICA3PP (1) | 1 |
| 2013 | Dealing with Reduction Operations Using Transactional MemoryabstractReductions are common operations in many real-world applications that may be responsible for a significant part of the computing time. Modern compilers implement parallel reductions by combining privatization, atomic operations and/or locks. In this paper we analyze how to address reductions in the transactional memory (TM) model, which is flourishing together with the modern shared-memory multicore-based parallel architectures. With this purpose, this paper studies which support needs to be added to a TM system to deal with reductions as a special case of conflicting memory accesses. Miguel A. Gonzalez-Mesa, Ricardo Quislant, Eladio Gutiérrez, Oscar G. Plata |
SBAC-PAD | 1 |