Daniel Thürck

dblp:130/6210 · also Daniel Thuerck · DBLP profile ↗
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4ranked-venue papers
2as first author
3since 2021 · last 2023
—ORCID · none

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Systems, architecture and hardware · 2 · 1 first-author · 1 since 2021Artificial intelligence and machine learning · 1 · 1 first-author · 1 since 2021Theory of computation · 1 · 1 since 2021
YearPublicationVenuePosition
2023 Learning Cuts via Enumeration Oracles
abstract
Cutting-planes are one of the most important building blocks for solving large-scale integer programming (IP) problems to (near) optimality. The majority of cutting plane approaches rely on explicit rules to derive valid inequalities that can separate the target point from the feasible set. Local cuts, on the other hand, seek to directly derive the facets of the underlying polyhedron and use them as cutting planes. However, current approaches rely on solving Linear Programming (LP) problems in order to derive such a hyperplane. In this paper, we present a novel generic approach for learning the facets of the underlying polyhedron by accessing it implicitly via an enumeration oracle in a reduced dimension. This is achieved by embedding the oracle in a variant of the Frank-Wolfe algorithm which is capable of generating strong cutting planes, effectively turning the enumeration oracle into a separation oracle. We demonstrate the effectiveness of our approach with a case study targeting the multidimensional knapsack problem (MKP).
Daniel Thürck, Boro Sofranac, Marc E. Pfetsch, Sebastian Pokutta
NeurIPS1
2021 Flynn's Reconciliation: Automating the Register Cache Idiom for Cross-accelerator Programming
abstract
A large portion of the recent performance increase in the High Performance Computing (HPC) and Machine Learning (ML) domains is fueled by accelerator cards. Many popular ML frameworks support accelerators by organizing computations as a computational graph over a set of highly optimized, batched general-purpose kernels. While this approach simplifies the kernels’ implementation for each individual accelerator, the increasing heterogeneity among accelerator architectures for HPC complicates the creation of portable and extensible libraries of such kernels. Therefore, using a generalization of the CUDA community’s warp register cache programming idiom, we propose a new programming idiom (CoRe) and a virtual architecture model (PIRCH), abstracting over SIMD and SIMT paradigms. We define and automate the mapping process from a single source to PIRCH’s intermediate representation and develop backends that issue code for three different architectures: Intel AVX512, NVIDIA GPUs, and NEC SX-Aurora. Code generated by our source-to-source compiler for batched kernels, borG, competes favorably with vendor-tuned libraries and is up to 2× faster than hand-tuned kernels across architectures.
Daniel Thürck, Nicolas Weber, Roberto Bifulco
ACM Trans. Archit. Code Optim.1
2021 Algorithm 1015: A Fast Scalable Solver for the Dense Linear (Sum) Assignment Problem
abstract
We present a new algorithm for solving the dense linear (sum) assignment problem and an efficient, parallel implementation that is based on the successive shortest path algorithm. More specifically, we introduce the well-known epsilon scaling approach used in the Auction algorithm to approximate the dual variables of the successive shortest path algorithm prior to solving the assignment problem to limit the complexity of the path search. This improves the runtime by several orders of magnitude for hard-to-solve real-world problems, making the runtime virtually independent of how hard the assignment is to find. In addition, our approach allows for using accelerators and/or external compute resources to calculate individual rows of the cost matrix. This enables us to solve problems that are larger than what has been reported in the past, including the ability to efficiently solve problems whose cost matrix exceeds the available systems memory. To our knowledge, this is the first implementation that is able to solve problems with more than one trillion arcs in less than 100 hours on a single machine.
Stefan Guthe, Daniel Thürck
ACM Trans. Math. Softw.2
2014 Using graphics processing units to investigate molecular coevolution
abstract
SUMMARY We present a massively parallel implementation of the computation of (co)evolutionary signals from biomolecular sequence alignments based on mutual information (MI) and a normalization procedure to neutral evolution. The MI is computed for two‐point and three‐point correlations within any multiple sequence alignment. We meet the high computational demand in the normalization procedure efficiently with an implementation on Graphics Processing Units (GPUs) using NVIDIA's CUDA framework. In particular, the normalization of the MI for three‐point ‘cliques’ of amino acids or nucleotides requires large sampling numbers in the normalization, which we achieve by using GPUs. GPU computation serves as an enabling technology here insofar as MI normalization is also possible using traditional computational methods [1] or cluster computation, but only GPU computation makes MI normalization for sequence analysis feasible in a statistically sufficient sample and in acceptable time given affordable commodity hardware. We illustrate (i) the computational efficiency and (ii) the biological usefulness of two‐point and three‐point MI by applications to the well‐known protein calmodulin and the variable surface glycoprotein (VSG) of Trypanosoma brucei, which are subject to involved evolutionary pressure. Here, we find striking coevolutionary patterns and distinct information on the molecular evolution of these molecules that question previous work that relied on non‐efficient MI computations. Copyright © 2013 John Wiley & Sons, Ltd.
Michael Waechter, Kathrin Jaeger, Daniel Thürck, Stephanie Weissgraeber, Sven Widmer, Michael Goesele, Kay Hamacher
Concurr. Comput. Pract. Exp.3